Id chip and ic card

ABSTRACT

The present invention provides an ID chip or an IC card in which the mechanical strength of an integrated circuit can be enhanced without suppressing a circuit scale. An ID chip or an IC card of the present invention has an integrated circuit in which a TFT (a thin film transistor) is formed from an insulated thin semiconductor film Further, an ID chip or an IC card of the present invention has a light-emitting element and a light-receiving element each using a non-single-crystal thin film for a layer conducting photoelectric conversion. Such a light-emitting element or a light-receiving element may be formed consecutively to (integrally with) an integrated circuit or may be formed separately and attached to an integrated circuit.

TECHNICAL FI FLD

The present invention relates to an ID chip or an IC card using anoptical communication.

BACKGROUND ART

An ID chip or an IC card that can transmit and receive data such asidentification information wirelessly has been put into practice invarious areas, and the expansion of its market is further anticipated asa communication information terminal of a new mode. An ID chip is alsocalled a wireless tag, a RFID (Radio frequency identification) tag or anIC tag. In general, an ID chip or an IC card having an antenna and anintegrated circuit (IC chip) formed by using a semiconductor substrateis put to practical use at present.

DISCLOSURE OF INVENTION

A semiconductor substrate which is employed to form an integratedcircuit is poor in flexibility, and its mechanical strength is low. Themechanical strength can be improved to some extent by reducing the areaof an integrated circuit itself. In this case, however, securing acircuit scale is difficult and the application of an ID chip or an ICcard is limited, which is not favorable. Therefore, it is not preferablethat the area of an integrated circuit is randomly reduced when securingthe circuit scale of the integrated circuit is considered to beimportant, and thus the enhancement of the mechanical strength islimited.

The present invention has been made in view of the above describedproblems. It is an object of the present invention to provide an ID chipor an IC card in which the mechanical strength of an integrated circuitcan be enhanced without suppressing a circuit scale.

An ID chip or an IC card of the present invention has an integratedcircuit in which a TFT (a thin film transistor) is formed from aninsulated thin semiconductor film. Further, an ID chip or an IC card ofthe present invention has a light-emitting element and a light-receivingelement using a non-single-crystal thin film for a layer conductingphotoelectric conversion. Such a light-emitting element or alight-receiving element may be formed consecutively to (integrally with)an integrated circuit or may be formed separately and attached to anintegrated circuit.

Note that an integrated circuit, a light-emitting element and alight-receiving element may be formed directly on a substrate, or may beformed on a substrate, then separated therefrom, and attached to anothersubstrate that is prepared separately.

The light-receiving element can convert a first signal sent from areader/writer to an electrical signal (a first electrical signal) andsend the first electrical signal to an integrated circuit. Theintegrated circuit operates in accordance with the first electricalsignal sent from the light-receiving element. Specifically, theintegrated circuit can generate a second electrical signal to betransmitted to a reader/writer and send it to a light-emitting element.The light-emitting element can convert the second electrical signaltransmitted from the integrated circuit to a second optical signal andsend the second optical signal to the reader/writer.

An ID chip or an IC card of the present invention can adopt a modehaving an antenna as well as an integrated circuit, a light-emittingelement and a light-receiving element. A chip of the present inventionon which an antenna is mounted is also called a radio frequency chip.The integrated circuit can generate a power supply voltage fromalternating voltage generated by an antenna. Note that the antenna maybe formed on the same substrate as the integrated circuit or may beformed separately from the integrated circuit and then electricallyconnected to the integrated circuit. If an ID chip or an IC card of thepresent invention has no antenna, the integrated circuit has aconnection terminal for electrically connecting with an antenna.

Alternatively, an ID chip or an IC card of the present invention mayhave a battery instead of an antenna.

Further, an ID chip, an IC card or a radio frequency chip of the presentinvention is also called a semiconductor device.

The attachment of an integrated circuit to a substrate may, for example,be carried out according to various kinds of methods as follows: a metaloxide film is formed between a high heat resistant substrate and anintegrated circuit, and the metal oxide film is crystallized andweakened to separate the integrated circuit, thereby attaching theintegrated circuit to an object; a separation layer is provided betweena high heat resistant substrate and an integrated circuit, theseparation layer is removed by laser irradiation or by etching toseparate the integrated circuit, thereby attaching the integratedcircuit to an object; a high heat resistant substrate over which anintegrated circuit is formed is mechanically removed or is removed byetching using a solution or a gas to separate the integrated circuit,thereby attaching the integrated circuit to an object.

Integrated circuits, which are formed separately, may be attached to oneanother to stack the integrated circuits such that the scale of thecircuits or the memory capacity may be increased. Since the respectiveintegrated circuits are dramatically thin in thickness as compared withan ID chip manufactured using a semiconductor substrate, the mechanicalstrength of an ID chip can be maintained to some extent even when theplural integrated circuits are stacked. The stacked integrated circuitscan be connected- to one another by using a known connection method suchas a flip chip method, a TAB (tape automated bonding) method or a wirebonding method.

A TFT is used in an integrated circuit, a non-single-crystal thin filmis used for a layer conducting photoelectric translation in alight-emitting element and a light receiving element, thereby making anID chip drastically thinner. Since the integrated circuit, thelight-emitting element and the light-receiving element do not need asemiconductor substrate, a flexible substrate can be used. Therefore,high mechanical strength can be obtained without reducing the area,unlike an integrated circuit using a semiconductor substrate. Therefore,the mechanical strength of an integrated circuit can be enhanced withoutsuppressing the circuit scale, and the application range of an ID chipor an IC card can be enlarged.

Furthermore, according to the present invention, since the integratedcircuit is formed using the electrically-isolated TFT, a parasitic diodeis difficult to be formed between the integrated circuit and thesubstrate, unlike a transistor formed over a semiconductor substrate.Therefore, a large amount of current does not flow through a drainregion due to a potential of an alternating-current signal that isapplied to a source region or the drain region, which rarely causes thedeterioration or breakdown. The present invention includes anadvantageous effect that radio waves are seldom blocked as compared withan integrated circuit formed by using a semiconductor substrate and thusattenuation of a signal due to blocking of the radio waves can beprevented.

When an integrated circuit, a light-emitting element and a lightreceiving element are formed integrally, a wiring for connecting theintegrated circuit with the light-emitting element or the lightreceiving element can be integrally formed with the integrated circuit.In addition, if the light-emitting element and the light-receivingelement are attached to the integrated circuit, the integrated circuit,the light-emitting element and the light-receiving element are easilyformed integrally, since the light-emitting element and thelight-receiving element are fowled by using thin films. Therefore, inboth cases, generation of connection failure can be suppressed informing an ID chip or an IC card. Further, if a flexible substrate isused, connection failure to be caused by stressing onto the substratecan be also suppressed, which leads to enhancing the reliability.

According to the present invention, transmission/reception of a signalis performed by optical communication and voltage of a power supply issupplied by radio waves. Therefore, it is possible that higher voltageof the power supply can be supplied to an integrated circuit as comparedwith the case of performing transmission/reception of a signal andsupplying the voltage of a power supply when only an optical signal isused. Therefore, communication range can be lengthened, and constraintin design of an integrated circuit by a power supply voltage can bereduced.

Moreover, a communication area can be more easily limited as comparedwith the case of performing transmission/reception of a signal andsupplying the voltage of a power supply when only radio waves are used.Therefore, overlapped communication areas and interfered signals can beprevented even when communication is conducted by radio waves having thesame frequency band as another communication device. And also, by usingoptical signals, high communication speed can be secured and a signalincluding large volumes of data can be sent and received. In addition,since transmission/reception of signals is above Radio Law in the caseof using optical signals, communication range can be lengthened as longas a power supply voltage is supplied surely.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are a perspective view and a block diagram of an ID chipaccording to one aspect of the present invention, respectively;

FIGS. 2A and 2B show an appearance and an internal structure of an ICcard according to one aspect of the present invention, respectively;

FIG. 3 is a block diagram showing a function of an IC card according toone aspect of the present invention;

FIGS. 4A and 4B are a block diagram showing a part that generates apower supply voltage in an integrated circuit and an appearance of an ICcard using a solar battery, respectively;

FIGS. 5A to 5D each show a manufacturing method of an ID chip accordingto one aspect of the present invention;

FIGS. 6A to 6C each show a manufacturing method of an ID chip accordingto one aspect of the present invention;

FIGS. 7A to 7C each show a manufacturing method of an ID chip accordingto one aspect of the present invention;

FIGS. 8A and 8B each show a manufacturing method of an ID chip accordingto one aspect of the present invention;

FIGS. 9A to 9C each show a manufacturing method of an ID chip accordingto one aspect of the present invention;

FIG. 10 shows a cross-section of an ID chip according to one aspect ofthe present invention;

FIGS. 11A and 11B each show a cross-section of an ID chip or an IC cardaccording to one aspect of the present invention;

FIGS. 12A and 12B each show a cross-section of an ID chip or an IC cardaccording to one aspect of the present invention;

FIGS. 13A and 13B each show a cross-section of an ID chip or an IC cardaccording to one aspect of the present invention;

FIGS. 14A to 14C each show a cross-section of a light-emitting elementof an ID chip or an IC card according to one aspect of the presentinvention;

FIGS. 15A to 15C are each a cross-section of a light-emitting element ofan ID chip or an IC card according to one aspect of the presentinvention;

FIGS. 16A to 16 C are each a cross-section of a TFT of an ID chip or anIC card according to one aspect of the present invention;

FIGS. 17A to 17D are each a diagram showing a method of manufacturing aplurality of integrated circuits from a large substrate, which are eachto be used as an ID chip or an IC card according to one aspect of thepresent invention;

FIGS. 18A to 18D each show a shape of a groove to be foamed when aplurality of integrated circuits formed on one substrate are separated;

FIGS. 19A to 19C each show how to use an ID chip according to one aspectof the present invention; and

FIGS. 20A and 20B each show how to use an ID chip according to oneaspect of the present invention.

BEST MODE FOR CARRYING OUT THE PRESENT INVENTION

Embodiment Modes according to the present invention will hereinafter bedescribed with reference to the accompanying drawings. The presentinvention can be carried out in many different modes, and it is easilyunderstood by those skilled in the art that modes and details hereindisclosed can be modified in various ways without departing from thespirit and the scope of the present invention. It should be noted thatthe present invention should not be interpreted as being limited to thedescription of the embodiment modes given below.

A structure of an ID chip according to the present invention will bedescribed with reference to FIGS. 1A and 1B. FIG. 1A is a perspectiveview of one mode of the ID chip according to the present invention.Reference numeral 100 denotes an integrated circuit, 101 denotes alight-receiving element, 102 denotes a light-emitting element, and 103denotes an antenna. The light-receiving element 101, the light-emittingelement 102 and the antenna 103 are all electrically connected to theintegrated circuit 100. The integrated circuit 100, the light-receivingelement 101, the light-emitting element 102 and the antenna 103 areformed on a substrate 104. A cover material 105 overlaps the substrate104, while sandwiching the integrated circuit 100, the light-receivingelement 101, the light-emitting element 102 and the antenna 103therebetween.

In FIG. 1A, the antenna 103, in addition to the integrated circuit 100,is sandwiched between the substrate 104 and the cover material 105.However, the present invention is not limited to this structure. Forexample, the antenna 103 may be formed on the side opposite to thesubstrate 104 with respect to the cover material 105.

An opening portion may be formed in the cover material 105 and theintegrated circuit 100 may be electrically connected to the antenna 103through the opening portion.

The ID chip of the present invention does not necessarily have theantenna 103. If the antenna 103 is not included in the ID chip, aconnection terminal for electrically connecting the antenna 103 isprovided for the ID chip.

FIG. 1A shows an example of enhancing the mechanical strength of the IDchip by using the cover material 105. However, the ID chip of thepresent invention does not necessarily have the cover material 105. Forexample, the integrated circuit 100, the light-receiving element 101,the light-emitting element 102 and the antenna 103 may be covered withresin or the like, thereby enhancing the mechanical strength of the IDchip.

FIG. 1B is a block diagram showing a functional structure of the ID chipof the present invention shown in FIG. 1A.

The integrated circuit 100 includes a rectification circuit 110 forrectifying alternating voltage generated in the antenna 103, and a powersupply circuit 111 for generating direct-current power supply voltagefrom the rectified voltage. Note that reference numeral 118 in FIG. 1Bcorresponds to a capacitor connected to opposite terminals of theantenna 103. The power supply voltage generated in the power supplycircuit 111 is supplied to various circuits in the integrated circuit100.

Further, the integrated circuit 100 includes a demodulation circuit 112for demodulating an electrical signal sent from the light-receivingelement 101, a logic circuit 113 conducting various arithmeticoperations by using the demodulated electrical signal in thedemodulation circuit 112, a memory 114 storing various data including aprogram, and a memory control circuit 115 that specifies an address ofthe memory 114 depending on a signal from the logic circuit 113 andwrites in or reads out data. In addition, the logic circuit 113 cangenerate an electrical signal to be transmitted to a reader/writer byusing various arithmetic operations or data stored in the memory 114.The electrical signal generated in the logic circuit 113 is converted toan optical signal in the light-emitting element 102 and transmitted tothe reader/writer.

FIG. 1B shows an example of the integrated circuit 100 having one logiccircuit 113, but the present invention is not limited to this structure.A plurality of logic circuits 113 may be provided in accordance with thecontent of arithmetic operations conducted in the logic circuit 113. Inaddition, the electrical signal converted from the optical signal in thelight-receiving element 101 may be amplified in an amplifier 116 beforeit is demodulated in the demodulation circuit 112. Alternatively, theelectrical signal generated in the logic circuit 113 may be amplified inthe amplifier 117 before it is sent to the light-emitting element 102.

One memory 114 is not necessarily used and a plurality of memories maybe used. Various semiconductor memories such as DRAM, SRAM, a flashmemory, ROM or FRAM (a registered trademark) can be used. The memory 114can be used as an operation area at the time of arithmetic operation.

In FIG. 1B, an oscillation circuit that can generate alternatingvoltage, and a modulation circuit that gives modulation to thealternating voltage generated in the oscillation circuit according tothe electrical signal generated in the logic circuit 113 may beincluded. In this case, the light-emitting element 102 can convert themodulated alternating voltage to an optical signal and the opticalsignal can be transmitted to the reader/writer.

The method for transmitting radio waves for supplying voltage of a powersupply is not limited to the electromagnetic coupling method as shown inFIGS. 1A and 1B. An electromagnetic induction method, a microwave methodand other transmitting methods may be used.

An insulated TFT is used for the integrated circuit 100. Various kindsof semiconductor elements can be used without being limited to a TFT asthe semiconductor element used in the integrated circuit 100. Inaddition to a TFT, for example, a memory element, a diode, aphotoelectric conversion element, a resistor element, a coil, acapacitor element, an inductor and the like can typically be employed.

A structure of an IC card according to the present invention will bedescribed with reference to FIGS. 2A, 2B and 3. FIG. 2A shows anappearance of the IC card according to the present invention. Referencenumeral 201 denotes a card body, 202 denotes a pixel portion of adisplay device 207 installed in the card body 201, 203 denotes alight-receiving element and 204 denotes a light-emitting element.

FIG. 2B shows a configuration of a substrate 205 included in the cardbody shown in FIG. 2A. An integrated circuit 206 formed by using a thinsemiconductor film, the light-receiving element 203, the light-emittingelement 204, the display device 207 and the antenna 208 are formed onthe substrate 205.

FIG. 2B shows an example in which the antenna 208 is formed togetherwith the integrated circuit 206, the light receiving element 203 and thelight-emitting element 204, but an IC card of the present invention isnot limited to this configuration. An antenna that is preparedseparately from the integrated circuit 206 may be electrically connectedto the integrated circuit 206. In this case, for example, a materialformed by winding a copper wire or the like in a coil and pressing itsandwiched by two plastic films, each having a thickness of about 100um, can be used as the antenna.

Only one antenna 208 is used for one IC card in FIG. 2B, but a pluralityof antennas 208 may be used.

FIGS. 2A and 2B each show the structure of the IC card having thedisplay device 207, but the present invention is not limited to thisstructure and the display device is not necessarily provided. However, adisplay device is provided, and thus, it is possible to display data ofa photograph of a human face in the display device and to make replacingthe photograph of a human face more difficult as compared with the caseof using the printing method. Moreover, information other than thephotograph of a human face can be displayed and a higher function ICcard can be obtained.

FIG. 3 is a block diagram showing a functional configuration of the ICcard of the present invention shown in FIG. 2B.

The integrated circuit 206 includes a rectification circuit 210 and apower supply circuit 211, like the ID chip shown in FIG. 1B. Referencenumeral 221 corresponds to a capacitor connected between oppositeterminals of the antenna 208. The integrated circuit 206 includes thedemodulation circuit 212, the logic circuit 213, the memory 214 and thememory control circuit 215. Further, the integrated circuit 206 mayinclude an amplifier 216 for amplifying an electrical signal before theelectrical signal is demodulated in the demodulation circuit 212, and anamplifier 217 for amplifying an electrical signal before the electricalsignal is transmitted to the light-emitting element 204. Specificstructures and operations of various circuits included in thisintegrated circuit 206 can be referred to the description of FIG. 1B.

In FIG. 3, as for the IC card of the present invention shown in FIG. 2B,the integrated circuit 206 includes a control circuit 218 for generatingvarious signals to be transmitted to the display device 207. A signalgenerated in the control circuit 218 is transmitted to a signal linedriver circuit 219 and a scanning line driver circuit 220 of the displaydevice 207. The operation of the pixel portion 202 is controlled by thesignal line driver circuit 219 and the scanning line driver circuit 220,and thus an image can be displayed on the pixel portion 202.

Note that the IC card shown in FIG. 3 may include an oscillation circuitthat can generate alternating voltage, and a modulation circuit to addmodulation to the alternating voltage generated in the oscillationcircuit according to an electrical signal generated in the logic circuit213. In this case, the light-emitting element 204 can convert themodulated alternating voltage to an optical signal and transmit theelectrical signal to the reader/writer.

The method for transmitting radio waves for supplying voltage of a powersupply is not limited to the electromagnetic coupling method as shown inFIGS. 2B and 3. An electromagnetic induction method, a microwave methodand other transmitting methods may be used.

An insulated TFT is used for the integrated circuit 206. Various kindsof semiconductor elements can be used without being limited to a TFT asthe semiconductor element used in the integrated circuit 206. Inaddition to a TFT, for example, a memory element, a diode, aphotoelectric conversion element, a resistor element, a coil, acapacitor element, an inductor and the like can typically be employed.

In the ID chips or IC cards shown in FIGS. 1A, 1B, 2A, 2B and 3, a powersupply voltage is supplied by radio wave, but the present invention isnot limited to this structure. A power supply voltage may be supplied tothe integrated circuit by using a battery instead of the antenna. Only aportion that generates power supply voltage in the integrated circuit isshown in a block diagram of FIG. 4A. In FIG. 4A, reference numeral 301denotes a battery and 302 denotes a power supply circuit. The powersupply circuit can generate power supply voltage having a value (height)necessary for various circuits by using a power supply voltage suppliedfrom the battery 301. Note that a chemical cell, a photovaltaic cell andthe like can be employed as the battery 301.

FIG. 4B shows an appearance of an IC card using a solar battery 303 thatis a kind of photovoltaic cells. The IC card can be used by using thesolar battery 303 instead of replacing the battery or charging thebattery. A battery for assisting power supply voltage may be used forthe ID chip or IC card in addition to the antenna.

A specific manufacturing method of the ID chip of the present inventionwill described. In this embodiment mode, an insulated TFT and aphotodiode used as a light-receiving element are shown as examples ofsemiconductor elements. However, the semiconductor element used in theintegrated circuit is not limited to these examples and various circuitelements can be used.

As shown in FIG. 5A, a separation layer 501 is formed by a sputteringmethod on a heat resistant substrate (a first substrate) 500. Forexample, glass substrates such as a barium borosilicate glass and analumino borosilicate glass, a quartz substrate, a ceramic substrate andthe like can be used for the first substrate 500. In addition, a metalsubstrate including a stainless (SUS) substrate or a semiconductorsubstrate on which an insulating film is formed may be used. A substratemade of synthetic resin having flexibility such as plastic generally hasa tendency in which the allowable temperature limit is lower than theabove described substrates, but it can be used as long as it can resistthe processing temperature in the manufacturing steps.

An amorphous silicon film, a polycrystalline silicon film, a singlecrystal silicon film, a micro crystalline silicon film (including asemiamorphous silicon film) and the like which mainly include siliconcan be used for the separation layer 501. The separation layer 501 canbe formed by a sputtering method, a low pressure CVD method, a plasmaCVD method or the like. In this embodiment mode, an amorphous silicon ofabout 50 nm thick is formed by a low pressure CVD method and is used asthe separation layer 501. The separation layer 501 is not limited tosilicon and a material that can be removed selectively by etching may beused. The thickness of the separation layer 501 is preferably 50 nm to60 nm. The thickness of semiamorphous silicon may be 30 nm to 50 nm.

A base film 502 is formed over the separation layer 501. The base film502 is provided to prevent an alkali metal such as Na or an alkali earthmetal contained in the first substrate 500 from diffusing into thesemiconductor film and adversely affecting characteristics of thesemiconductor element such as a TFT. In addition, the base film 502 alsohas a function of protecting the semiconductor element in the later stepof separating the semiconductor element. The base film 502 may have asingle layer or a plurality of laminated insulating films. Therefore,the base film 502 is formed by using an insulating film such as siliconoxide, silicon nitride or silicon nitride oxide that can prevent analkali metal or an alkali earth metal from diffusing into thesemiconductor film.

In this embodiment mode, a SiON film of 100 nm thick, a SiNO film of 50nm thick, and a SiON film of 100 nm are sequentially formed to form thebase film 502, and the material, thickness, number of laminations ofeach film are not limited thereto. For example, instead of the SiON filmin the lower layer, siloxane resin of 0.5 μm to 3 μm in film thicknessmay be formed by a spin coating method, a slit coating method, a dropletdischarging method, a printing method or the like. Instead of the SiNOfilm in the middle layer, a silicon nitride film (such as SiNx or Si₃N₄)may be formed. Instead of the SiON film in the upper layer, a SiO₂ filmmay be used. In addition, the thickness of each film is preferably 0.05μm to 3 μm and can be freely selected from the range of 0.05 μm to 3 μm.

Alternatively, the lower layer of the base film 502 that is closest tothe separation layer 501 may be fowled from a SiON film or a SiO₂ film,the middle layer may be formed from siloxane resin, and the upper layermay be formed from a SiO₂ film.

The droplet discharging method is a method for forming a predeterminedpattern by discharging droplets containing a predetermined compositionfrom a minute hole, which includes an ink-jetting method. The printingmethod includes a screen-printing method, an offset printing method andthe like.

The silicon oxide film can be fowled by a thermal CVD method, a plasmaCVD method, an atmospheric pressure CVD method, a bias ECRCVD method orthe like using a mixture gas of SiH₄/O₂, TEOS (tetraethoxysilane)/O₂ orthe like. In addition, the silicon nitride film can typically be formedby a plasma CVD method using a mixture gas of SiH₄/NH₃. In addition, thesilicon oxynitride film (SiOxNy: x>y) and the silicon nitride oxide film(SiNxOy: x>y) can typically be formed by a plasma CVD method using amixture gas of SiH₄/N₂O.

A semiconductor film 503 is formed over the base film 502. Preferably,the semiconductor film 503 is fowled without being exposed to the airafter forming the base film 502. The thickness of the semiconductor film503 is set to be 20 to 200 nm (desirably, 40 to 170 nm, more preferably,50 to 150 nm). The semiconductor film 503 may be an amorphoussemiconductor, a semiamorphous semiconductor or a polycrystallinesemiconductor. Silicon germanium as well as silicon can also be used asthe semiconductor film. When using silicon germanium, the concentrationof germanium is preferably set to be about 0.01 to 4.5 atomic %.

The semiconductor film 503 may be crystallized by a known method. Alaser crystallization method using laser light and a crystallizationmethod using a catalytic element are given as the known crystallizationmethods. Alternatively a method that combines the crystallization methodusing a catalytic element and the laser crystallization method can beused. When an excellent heat resistant substrate like quartz is used asthe first substrate 500, any of a thermal crystallization method usingan electrically-heated furnace, a lamp annealing crystallization methodusing infrared light, and the crystallization method using a catalyticelement may be combined with high temperature annealing of about 950° C.as a crystallization method. In the case of the laser crystallization,for example, the semiconductor film 503 is subjected to thermalannealing at 500° C. for one hour to enhance a resistance property withrespect to a laser beam prior to performing laser crystallization. Acontinuous wave solid-state laser is used and a laser beam with secondto fourth harmonics of the fundamental wave is irradiated to obtain acrystal having a large grain size. Typically, for instance, the secondharmonic (532 nm) or the third harmonic (355 nm) of Nd:YVO₄ laser(fundamental wave with 1064 nm) is preferably used. Concretely, a laserbeam emitted from the continuous wave YVO₄ laser is converted into aharmonic by a nonlinear optical element to obtain a laser beam with 10 Woutput. The laser beam is preferably formed to have a rectangular shapeor an elliptical shape on a surface of the semiconductor film 503 to beirradiated with the laser beam. In this case, the power density of about0.01 to 100 MW/cm² (preferably, 0.1 to 10 MW/cm²) is required. Thescanning rate is approximately set to be 10 to 2,000 cm/sec to irradiatethe semiconductor film.

While the oscillation frequency of a pulsed laser beam is set to be 10MHz or more, laser crystallization may be carried out using a muchhigher frequency band than a frequency band of several tens Hz toseveral hundreds Hz, which is generally used. The period fromirradiating a pulsed laser beam onto the semiconductor film to curingthe semiconductor film completely is considered to be several tens nsecto several hundreds nsec. By utilizing the above-mentioned frequencyband, the next pulsed laser beam can be irradiated to the semiconductorfilm until the semiconductor film is melted due to irradiation of alaser beam and then solidified. Therefore, a solid-liquid interface canbe moved continuously in the semiconductor film, so that thesemiconductor film having crystal grains, which are continuously grownin the scanning direction, is formed. Specifically, an aggregate of thecrystal grains each of which has a width of 10 to 30 μm in a scanningdirection and a width of 1 to 5 μm in a direction perpendicular to thescanning direction can be obtained. The semiconductor film in whichalmost no crystal grain boundaries are formed in the channel directionof a TFT can be formed by forming the single crystal grains growing inthe scanning direction.

As for the laser crystallization, laser light of the fundamental wave ofa continuous wave laser and laser light of the harmonic of a continuouswave laser may be irradiated in parallel. Alternatively, laser light ofthe fundamental wave of a continuous wave laser and laser light of theharmonic of a pulsed laser may be irradiated in parallel.

A laser beam may be irradiated under an inert gas atmosphere such asrare gas and nitrogen.

By the above described laser irradiation, the semiconductor film 503with improved crystallinity is formed. Note that a polycrystallinesemiconductor may in advance be formed by a sputtering method, a plasmaCVD method, a thermal CVD method or the like.

The semiconductor film 503 is crystallized in this embodiment mode, butan amorphous silicon film or a microcrystalline semiconductor film maybe used in the next process without performing the crystallization. ATFT using an amorphous semiconductor or a microcrystalline semiconductorneeds fewer manufacturing steps than a TFT using a polycrystallinesemiconductor, and thus, has advantageous effects of reducing costs andenhancing yield.

The amorphous semiconductor can be obtained by performing glow dischargedecomposition of silicide gas. Typically, SiH₄ and Si₂H₆ are cited asexamples for the silicide gas. These silicide gases may be diluted withhydrogen or hydrogen and helium.

A semiamorphous semiconductor has an intermediate structure between anamorphous structure and a crystalline structure (including a singlecrystalline structure, and a polycrystalline structure), and a thirdstate that is stable with respect to free energy. Such a semiamorphoussemiconductor has a crystal structure that includes a short range orderand lattice distortion. Crystal grains of 0.5 nm to 20 nm in size can becontained and dispersed in a non-single crystal semiconductor. As forthe semiamorphous semiconductor, the Raman spectrum shifts to the lowerside of a wave number of 520 cm⁻¹, and a diffraction peak of (111) and(220) derived from a silicon crystal lattice is observed in x-raydiffraction. Further, the semiamorphous semiconductor contains hydrogenor halogen of 1 atom % or more for terminating a dangling bond. Herein,such the semiconductor is referred to as a semiamorphous semiconductor(SAS) for convenience. When a rare gas element such as helium, argon,krypton, or neon is mixed into a SAS (semiamorphous semiconductor), thelattice distortion is further increased and the stability is thusenhanced, thereby obtaining an excellent semiamorphous semiconductor(SAS).

The SAS is formed by glow discharge decomposition of silicide gas. SiH₄is a representative silicide gas. In addition to SiH₄, Si₂H₆, SiH₂Cl₂,SiHCl₃, SiCl₄, SiF₄ and the like can be used as the silicide gas. Thesilicide gas may also be diluted with hydrogen, or a mixture of hydrogenand one or more rare gas elements selected from helium, argon, krypton,and neon so that the SAS can be easily formed. The dilution ratio ispreferably set to be in the range of 1:2 to 1:1,000. In addition, acarbide gas such as CH₄ and C₂H₆ or germanium gas such as GeH₄ or GeF₄,or F₂ may be mixed in the silicide gas so that the width of the energyband may be adjusted in the range of 1.5 to 2.4 eV or 0.9 to 1.1 eV.

In the case of using a gas containing a mixture of SiH₄ and H₂ or a gascontaining a mixture of SiH₄ and F₂, for example, when a TFT ismanufactured using the semiamorphous semiconductor, the subthresholdcoefficient (S value) of the TFT can be set to be 0.35 V/sec or lower,typically, 0.25 to 0.09V/sec, and the mobility thereof can be set to be10 cm²/Vsec. For example, when a 19-stage ring oscillator is formed byusing the TFT using the above semiamorphous semiconductor, acharacteristic of the oscillation frequency of 1MH or more, preferably100 MHz or more at the power supply voltage of 3 to 5 V can be obtained.In addition, the delay time for each stage of an inverter can be 26 ns,preferably 0.26 ns or less at the power supply voltage of 3 to 5 V.

As shown in FIG. 5B, the semiconductor film 503 is patterned to formisland-like semiconductor films 504 to 507. A gate insulating film 508is formed to cover the island-like semiconductor films 504 to 507. Afilm including silicon nitride, silicon oxide, silicon nitride oxide orsilicon oxynitride as a single layer or a lamination layer can be formedas the gate insulating film 508 by a plasma CVD method or a sputteringmethod. In laminating the films, for example, a three-layer structure inwhich a silicon oxide film, a silicon nitride film and a silicon oxidefilm are stacked in this order on the substrate is preferably employed.

After forming the gate insulating film 508, a heat treatment may becarried out at 300 to 450° C. for 1 to 12 hours under an atmospherecontaining 3 to 100% hydrogen so as to hydrogenate the island-likesemiconductor films 504 to 507. As another hydrogenation method, plasmahydrogenation (using hydrogen excited by plasma) may be performed.Through the hydrogenation step, dangling bonds can be terminated by thethermally excited hydrogen. If defects are caused in the semiconductorfilm by bending a second substrate 545 after attaching the semiconductorelements to the flexible second substrate 545 in the subsequent step,the concentration of hydrogen contained in, the semiconductor film isset to be 1×10¹⁹ to 1×10²² atoms/cm³, preferably, 1×10¹⁹ to 5×10²⁰atoms/cm³ by hydrogenation, so that the defects can be terminated by thehydrogen contained in the semiconductor film. In addition, halogen maybe contained in the semiconductor film to terminate the defects.

Next, gate electrodes 509 to 512 are formed as shown in FIG. 5C. In thisembodiment mode, after laminating Si and W by a sputtering method, thegate electrodes 509 to 512 are formed by etching using resist 513 as amask. Of course, the material, structure, and manufacturing method ofthe gate electrodes 509 to 512 are not limited thereto and can beselected appropriately. For example, a lamination structure of NiSi(nickel silicide) with Si with an n-type impurity added, or a laminationstructure of TaN (tantalum nitride) with W (tungsten) may be employed.In addition, the gate electrode may be formed as a single layer ofvarious conductive materials.

A mask of SiOx or the like may be used instead of a resist mask. In thiscase, a step of patterning is added to form a mask of SiOx, SiON or thelike (it is called a hard mask) but the thickness of the mask is reducedless in etching than that of a resist mask. Thus, the gate electrodes509 to 512 having a desired width can be formed. Alternatively, the gateelectrodes 509 to 512 may be formed selectively by a droplet dischargingmethod without using the resist 513.

Various materials can be selected as the conductive material accordingto the function of the conductive film. If the gate electrode and theantenna are formed simultaneously, materials thereof may be selectedconsidering the function.

Using an etching method, a mixture of gases CF₄, Cl₂ and O₂ or a Cl₂ gasis used as the etching gas in forming the gate electrodes, but theetching gas is not limited to these.

As shown in FIG. 5D, the island-like semiconductor film 505 to become ap-channel 1 is covered with resist 514 and an n-type impurity element(typically, phosphorus or arsenic) is doped into the island-likesemiconductor films 504, 506 and 507 to form a low concentration regionusing the gate electrodes 509, 511 and 512 as masks (a first dopingstep). The condition of the first doping step is as follows: the doseamount of 1×10¹³ to 6×10¹³/cm², and the accelerating voltage of 50 to 70keV. However, the condition is not limited thereto. Pairs of lowconcentration impurity regions 515 to 517 are formed in the island-likesemiconductor films 504, 506 and 507 by doping through the gateinsulating film 508 by this first doping step. Note that the firstdoping step may be conducted without covering the island-likesemiconductor 505 to become a p-channel TFT with resist.

Next, as shown in FIG. 6A, after resist 514 is removed by ashing or thelike, a new resist 518 is formed to cover the island-like semiconductorfilms 504, 506 and 507 to become n-channels TFT. An impurity element(typically, boron) imparting a p-type conductivity is doped into theisland-like semiconductor film 505 to form a high concentration regionusing the gate electrode 510 as a mask (second doping step). Thecondition of the second doping step is as follows: the dose amount of1×10¹⁶ to 3×10¹⁶/cif², and the accelerating voltage of 20 to 40 keV. Apair of p-type high concentration impurity regions 519 is formed in theisland-like semiconductor film 505 by doping through the gate insulatingfilm 508 by performing the second doping step.

Next, as shown in FIG. 6B, after the resist 518 is removed by asking orthe like, an insulating film 520 is formed to cover the gate insulatingfilm 508 and the gate electrodes 509 to 512. In this embodiment mode, anSiO₂ film of 100 nm thick is formed by a plasma CVD method. After that,the insulating film 520 and the gate insulating film 508 are etchedpartially by an etchback method. As shown in FIG. 6C, sidewalls 521 to524 are formed in a self-alignment manner to be in contact with thesidewalls of the gate electrodes 509 to 512. A mixture gas of CHF₃ andHe is employed as the etching gas. Note that the step of forming thesidewalls is not limited thereto.

When forming the insulating film 520, there is a risk that an insulatingfilm is also formed on the rear surface of the first substrate 500. Inthis case, the insulating film formed on the backside of the firstsubstrate 500 may be selectively etched and removed by using resist. Inthis case, the insulating film formed on the rear surface may be etchedand removed together with the insulating film 520 and the gateinsulating film 508 in the process of forming the sidewalls 521 to 524by the etchback method.

As shown in FIG. 7A, a new resist 525 is formed to cover the island-likesemiconductor 505 to become a p-channel TFT, an n-type impurity element(typically, P or As) is doped to form a high concentration region usingthe gate electrodes 509, 511 and 512 and the sidewalls 521, 523 and 524as masks (the third doping step). The condition of the third doping stepis as follows: the dose amount of 1×10¹³ to 5×10¹⁵/cm², and theaccelerating voltage of 60 to 100 keV. Pairs of n-type highconcentration impurity regions 526 to 528 are formed in the island-likesemiconductor films 504, 506 and 507 by performing the third dopingstep.

When n-type impurities are doped to form a high concentration region,the sidewalls 521, 523 and 524 function as masks to form a lowconcentration impurity region or an off-set region in which doping isnot done in a lower part of the sidewalls 521, 523 and 524. Therefore,the size of the sidewalls 521, 523 and 524 may be adjusted byappropriately changing the thickness of the insulating film 520, and theconditions of an etchback method in forming the sidewalls 521, 523 and524, so as to control the width of the low concentration impurity regionor the off-set region.

After the resist 525 is removed by asking or the like, thermalactivation may be carried out to the impurity region. For example, aSiON film of 50 nm is formed and then may be exposed to a heat treatmentin a nitrogen atmosphere at 550° C. for four hours. A SiNx filmcontaining hydrogen is formed to be 100 nm thick, and then, is exposedto a heat treatment in a nitrogen atmosphere at 410° C. for one hour tocorrect defects of the polycrystalline semiconductor film. This iscalled, for example, a hydrogen treatment process, which terminatesdangling bonds in the polycrystalline semiconductor film.

Through the above described series of steps, n-channel TFTs 529, 531 and532 and a p-channel TFT 530 are formed. Note that the n-channel TFT 531can be used as a photodiode. In the above described manufacturing steps,the conditions of an etchback method are changed appropriately and thesizes of the sidewalls are adjusted to form TFTs having a channel lengthof 0.2 μm to 2 μm. It is noted that, in this embodiment mode, a bottomgate structure (an inverted staggered structure) may be employedalthough a top gate structure is employed for the TFTs 529 to 532.

Additionally, thereafter, a passivation film to protect the TFT 529 to532 may be formed. Thus, the passivation film is preferably formed byusing silicon nitride, silicon nitride oxide, aluminum nitride, aluminumoxide, silicon oxide or the like which can prevent an alkali metal or analkali earth metal from entering the TFTs 529 to 532. Specifically, forexample, a SiON film of about 600 nm thick can be used for thepassivation film. In this case, the hydrogen treatment process may beconducted after forming the SiON film. Like this, a three-layerstructure of insulating films SiON\SiNx\SiON stacked in this order isformed over the TFT 529 to 532, but the structure or materials thereofare not limited thereto. By the above described structure, the TFT 529to 532 are covered with the base film 502 and the passivation film,thereby further preventing an alkali metal such as Na or an alkali earthmetal from diffusing into the semiconductor film used in a semiconductorelement and from adversely affecting characteristics of thesemiconductor element.

Next, a first interlayer insulating film 533 is formed to cover the TFTs529 to 532 as shown in FIG. 7B. Organic resin having heat-resistancesuch as polyimide, acryl or polyamide can be used for the firstinterlayer insulating film 533. Besides the organic resin, a lowdielectric constant material (a low-k material) or a resin containingSi—O—Si bond (hereinafter, referred to as a siloxane resin) or the likecan be used. Siloxane has a skeleton structure with a bond of silicon(Si) and oxygen (O). As a substitute thereof, an organic group includingat least hydrogen (such as alkyl group or aromatic hydrocarbon) is used.Further, a fluoro group may be used for the substitute. Also, an organicgroup including at least hydrogen and a fluoro group may be used for thesubstitute. In forming the first interlayer insulating film 533, aspin-coating method, a dipping method, a spray coating method, a dropletdischarging method (an ink-jet method, a screen-printing method, anoff-set printing method and the like) a doctor knife, a roll coater, acurtain coater, a knife coater, and the like can be employed dependingon the material of the interlayer insulating film. Further, an inorganicmaterial may be used. At this time, a silicon oxide film, a siliconnitride film, a silicon oxynitride film, a PSG (phosphorus silicateglass) film, a PBSG (phosphorus boron silicate glass) film, a BPSG(borophosphosilicate glass) film, an alumina film and the like can beused. Note that these insulating films may be laminated to form thefirst interlayer insulating film 533.

Further, in this embodiment mode, a second interlayer insulating film534 may be formed over the first interlayer insulating film 533. As forthe second interlayer insulating film 534, a film containing carbon suchas DLC (Diamond Like Carbon) or carbon nitride (CN), a silicon oxidefilm, a silicon nitride film, a silicon nitride oxide film, or the likecan be employed. As for the forming method, plasma CVD, atmosphericpressure plasma, or the like can be employed. Alternatively, aphotosensitive or nonphotosensitive organic material such as polyimide,acrylic, polyamide, resist, and benzocyclobutene, or a siloxane resinmay be employed.

Note that a filler may be mixed into at least one of the firstinterlayer insulating film 533 and the second interlayer insulating film534 in order to prevent film detachment or a crack of these films due tostress generated by a difference of a thermal expansion coefficientbetween the first interlayer insulating film 533 or the secondinterlayer insulating film 534 and a conductive material of a wiring orthe like formed at a subsequent step.

As shown in FIG. 7B, contact holes are formed in the first interlayerinsulating film 533 and the second interlayer insulating film 534.Wirings 535 to 541 connecting to the. TFTs 529 to 532 are twined. As foran etching gas for forming the contact hole, a mixed gas of CHF₃ and Heis employed, but the present invention is not limited to this. In thisembodiment mode, the wirings 535 to 541 are formed of Al. Here, thewirings 535 to 541 may be fowled to have a five-layer structure in whichTi, TiN, Al-Si, Ti and TiN are formed sequentially by sputtering.

By mixing Si into the Al layer, the generation of hillocks can beprevented during resist baking when the wiring is patterned. Instead ofthe Si, Cu of about 0.5% may be mixed. In addition, by sandwiching theAl-Si layer with Ti or TiN, hillock resistance can be further improved.At the patterning, the above-described hard mask of SiON or the like ispreferably employed. Note that the material and the forming method ofthese wirings are not limited to these, and the aforementioned materialfor totaling the gate electrode may be employed.

The wirings 535 and 536 are connected to the high concentration impurityregion 526 of the n-channel TFT 529; the wirings 536 and 537 to the highconcentration impurity region 519 of the p-channel TFT 530; the wirings538 and 539 to the high concentration impurity region 527 of then-channel TFT 531; and the wirings 540 and 541 to the high concentrationimpurity region 528 of the n-channel TFT 532, respectively.

As shown in FIG. 7C, a protective film 542 is foil ed over the secondinterlayer insulating film 534 to cover the wirings 535 to 541. Theprotective layer 542 is made from a material that can protect the IFI529 to 532 and the wirings 535 to 541 in removing the separation layer501 by etching in the subsequent step. For example, a water-soluble oralcohol-soluble epoxy resin, acrylate resin or silicon resin is whollyapplied to form the protective layer 542.

For forming the protective layer 542 in the embodiment mode, awater-soluble resin (VL-WSHL10 manufactured by Toagosei Co., Ltd.) isapplied by a spin coating method to have a thickness of 30 μm andexposed to light for 2 minutes so as to be cured temporarily. Then, thewater-soluble resin is further exposed to UV light from a rear face for2.5 minutes and from a top face for 10 minutes, i.e., for 12.5 minutesin total to be cured completely, thereby forming the protective layer542. When plural kinds of organic resins are laminated, they might bepartly dissolved to each other in coating or baking, or adhesion mightbe excessively increased depending on the solvents containing in theorganic resins. Therefore, when the second interlayer insulating film534 and the protective layer 542 are both made from organic resins thatare soluble in the same solvent, an inorganic insulating film (e.g., aSiN_(X) film, a SiN_(X)O_(Y) film, an AlN_(X) film or an AlN_(X)O_(Y)film) is preferably formed to cover the second interlayer insulatingfilm 534 such that the protective layer 542 is smoothly removed in thesubsequent step.

As shown in FIG. 8A, a groove 543 is formed to separate the ID chipsfrom one another. The groove 543 may be deep enough to expose theunderlying separation layer 501. The groove 543 can be fowled by dicing,scribing, or the like. When the ID chips formed over the first substrate500 is not necessarily divided, the groove 543 may not necessarily beformed.

As shown in FIG. 8B, the separation layer 501 is removed by etching. Inthe embodiment mode, halogen fluoride is used as an etching gas and thegas is introduced through the groove 543. In this embodiment mode, forexample, ClF₃ (chlorine trifluoride) is employed, and etching is carriedout under the conditions as follows: a temperature is set to be 350° C.;a flow rate, 300 sccm; a pressure, 799.8 Pa (6 Torr); and time, 3 hours.Further, ClF₃ gas mixed with nitrogen may be used. By using a halogenfluoride such as ClF₃, the separation layer 501 is selectively etched,so that the first substrate 500 can be separated from the TFTs 529 to532. Note that the halogen fluoride may be in either a gas state or aliquid state.

As shown in FIG. 9A, the separated TFTs 529 to 532 are attached to thesecond substrate 545 with an adhesive agent 544. A material that canattach the second substrate 545 to the base film 502 is employed for theadhesive agent 544. The following examples of various types of curingadhesive agents including a reactive curing adhesive agent, a thermalcuring adhesive agent, a light curing adhesive agent such as anultraviolet curing adhesive agent, an anaerobic curing adhesive agentand the like can be used as the adhesive agent 544.

As the second substrate 545, a glass substrate such as bariumborosilicate glass or alumino borosilicate glass or a flexible organicmaterial such as paper and plastics can be used. In addition, a flexibleinorganic material may be employed. As the plastic substrate, ARTON(manufactured by JSR Corporation) made from polynorbornene with a polarradical can be used. Also, the following materials can be cited as theplastic substrate: polyester typified by polyethylene terephthalate(PET), polyether sulfone (PES), polyethylene naphtbalate (PEN),polycarbonate (PC), nylon, polyether ether ketone (PEEK), polysulfone(PSF), polyetherimide (PEI), polyarylate (PAR), polybutyleneterephthalate (PBT), polyimide, acrylonitrile butadiene styrene resin,polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin andthe like. The second substrate 545 desirably has high thermalconductivity of about 2 to 30 W/mK in order to diffuse the heatgenerated from the integrated circuit.

Next, a bank 546 is fixated over the second interlayer insulating film534 to cover the wirings 535 to 541 as shown in FIG. 9B. The bank 546has an opening portion in which parts of the wirings 535 and 541 areexposed. In addition, the bank 546 can be fainted by using an organicresin film, an inorganic insulating film or a siloxane based insulatingfilm. Examples of the organic resin film include acryl, polyimide,polyamide, and the like. Examples of the inorganic resin film includesilicon oxide, silicon nitride oxide and the like. Specifically, aphotosensitive organic resin film is used for the bank 546, and the bank546 is formed so that the sidewall of the opening portion in which thewiring 541 is exposed has an inclined plane with a successive curvature.Therefore, it is possible to prevent connection of the wiring 541 and anelectrode 548 to be formed later. At the time, a mask can be formed by adroplet discharging method or a printing method. Alternatively, the bank546 itself can be formed by a droplet discharging method or a printingmethod.

Next, a light-emitting element 549 or an antenna 550 is formed. Thisembodiment mode shows a mode in which the light-emitting element 549 isformed first, but the antenna 550 may be formed first, or the antenna550 may be formed together at the same time as when the electrode 548 ofthe light-emitting element 549 is formed.

Before forming an electroluminescent layer 547 corresponding to a layerconducting photoelectric conversion, a heat treatment in an atmosphericair or a heat treatment in a vacuum atmosphere (vacuum baking) may beperformed in order to remove water, oxygen or the like absorbed by thebank 546 and the wiring 541. Specifically, the heat treatment isperformed in a vacuum atmosphere, with a substrate temperature of 200°C. to 450° C., preferably 250° C. to 300° C. for about 0.5 to 20 hours.It is desirably set the vacuum atmosphere at 3×10 ⁷ Ton or less, mostpreferably at 3×10⁻⁸ Torr or less if possible. In the case where theelectroluminescent layer 547 is formed after performing the heattreatment in the vacuum atmosphere, the reliability can be furtherimproved by setting the substrate in the vacuum atmosphere just beforeforming the electroluminescent layer 547. In order that a surface of thewiring 541, to be used as an anode or a cathode, is flattened, thesurface may be cleaned and polished by a CMP method with polyvinylalcohol porous body or the like before forming the vacuum baking. Inaddition, the surface of the wiring 541, to be used as an anode or acathode, may be exposed to ultraviolet irradiation, an oxygen plasmatreatment or the like after being polished by a CMP method.

The electroluminescent layer 547 is formed to be in contact with thewiring 541 in the opening portion of the bank 546. Theelectroluminescent layer 547 may be formed with a single layer or alamination layer. In this embodiment mode, since the wiring 541 is usedas the cathode, an electron injecting layer, an electron transportinglayer, a light emitting layer, a hole transporting layer, and a holeinjecting layer are sequentially formed over the wiring 541 when theelectroluminescent layer 547 is to be formed by using plural layers.Note that a hole injecting layer, a hole transporting layer, a lightemitting layer, an electron transporting layer, and an electroninjecting layer are sequentially formed to form the electroluminescentlayer 547 if the wiring 541 serves as the anode.

Note that a light-emitting element 549 that emits infrared light can beformed by appropriately changing the lamination structure of theelectroluminescent layer 547 and the electroluminescent materials usedfor the layers.

A color filter may be provided to transmit light having a particularwavelength range. The color filter includes a colored layer that cantransmit light of a particular wavelength range, or may include ashielding film that can shield visible light, in addition to the coloredlayer. The color filter may be formed over a cover material for sealingthe light-emitting element or over a substrate. In each case, thecolored layer or the shielding film can be formed by a printing methodor a droplet discharging method.

The electrode 548 is formed to cover the electroluminescent layer 547.The electrode 548 serves as an anode when the wiring 541 serves as acathode. On the contrary, when the wiring 541 serves as an anode, theelectrode 548 serves as a cathode. The manufacturing method of theelectrode 548 is preferably selected from a vapor deposition method, asputtering method, a droplet discharging method and the like dependingon the material.

The electroluminescent layer 547 can be formed by a droplet dischargingmethod even when using any one of the following compounds: a highmolecular weight organic compound, an intermediate molecular weightorganic compound, a low molecular weight organic compound, and aninorganic compound. An intermediate molecular weight organic compound, alow molecular weight organic compound, and an inorganic compound may beformed by a vapor deposition method. Note that the electroluminescentlayer 547 and the electrode 548 are formed in a region that is differentfrom a region in which an antenna 550 is to be formed later.

Other light-transmitting conductive oxide materials such as indium tinoxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO) and gallium-dopedzinc oxide (GZO) can be used as the anode. Further, the anode may beformed by using indium tin oxide including ITO and siliconoxide(hereinafter, ITSO), and indium oxide including silicon oxide inwhich zinc oxide (ZnO) is further mixed in the range of 2 to 20%. Inaddition to the other light-transmitting conductive oxide materials forthe anode, for example, a single layer of one or more of TiN, ZrN, Ti,W, Ni, Pt, Cr, Ag and Al; a lamination of a titanium nitride film and afilm mainly containing aluminum; a three-layer lamination of a titaniumnitride film, a film mainly containing aluminum and a titanium nitridefilm; and the like can be employed. Note that the anode is formed tohave the film thickness sufficient to transmit light (preferably, about5 nm to 30 nm) when light is extracted from the anode side in using amaterial other than the light-transmitting conductive oxide materials.

The cathode can be formed of a metal, an alloy, a conductive compound,or a mixture of these materials each having low work function.Specifically, the cathode can be formed of an alkali metal such as Li orCs; an alkali-earth metal such as Ca, Sr, or Mg; an alloy includingthese (such as Mg:Ag, Al:Li, or Mg:In); a compound of these (such asCaF₂ or CaN); or a rare-earth metal such as Yb or Er. When anelectron-injecting layer is provided, another conductive layer such asAl can be used. When the light is emitted from the cathode side, thecathode can be formed of another light-transmitting conductive oxidematerial such as the indium tin oxide (ITO), zinc oxide (ZnO), indiumzinc oxide (IZO), or gallium-doped zinc oxide (GZO). Moreover, thecathode may be formed of indium tin oxide including ITO and siliconoxide (ITSO), or indium oxide including silicon oxide in which zincoxide (ZnO) is further mixed in the range of 2 to 20%. In the case ofusing such light-transmitting conductive oxide materials, theelectron-injecting layer is preferably provided in theelectroluminescent layer 547. By forming the cathode to be thick enoughto transmit light (preferably from approximately from 5 nm to 30 nm)without using the light-transmitting conductive oxide material, thelight can be extracted from the cathode side. In this case, the sheetresistance of the cathode may be suppressed by forming alight-transmitting conductive film to contact the upper part or thelower part of the cathode by using the light-transmitting conductiveoxide material.

The second interlayer insulating film 534 is formed from silicon nitrideor silicon nitride oxide. A wiring 541 to be in contact with the secondinterlayer insulating film 534 is formed by using a conductive filmincluding a light transmitting conductive oxide material and siliconoxide such as ITSO. Thus, the luminance of the light-emitting element549 can be enhanced more than any material combination of the wiring 541and the second interlayer insulating film 534. Note that the abovedescribed vacuum baking is extremely effective for the case where ITSOis used as the wiring 541 since water is easily attached by siliconoxide included therein.

The wiring 541, the electroluminescent layer 547 and the electrode 548are overlapped in the opening portion of the bank 546 to form alight-emitting element 549.

The light from the light-emitting element 549 may be extracted from thewiring 541 side, from the electrode 548 side, or from the oppositesides. The material and thickness of each anode and cathode are selectedfrom the three structures depending on an intended structure.

A method for manufacturing of an antenna 550 is described next. Theantenna 550 may be formed simultaneously in forming the electrode 548 ofthe light-emitting element 549 by pattering a conductive film or may beformed by another manufacturing method. This embodiment mode shows anexample of forming the antenna 550 by a method different from themanufacturing method of the electrode 548.

As shown in FIG. 9B, the antenna 550 is formed on the bank 546. Theantenna 550 can be formed of a conductive material containing one ormore metals such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, Al, Fe, Co, Zn,Sn and Ni, or metal compounds thereof. The antenna 550 is connected tothe wiring 535. Although the antenna 550 is directly connected to thewiring 535 in FIG. 9B, the ID chip of the present invention is notlimited to this structure. For example, the antenna 550 and the wiring535 may be electrically connected to each other by using a wiring thatis separately formed.

The antenna 550 can be formed by a printing method, a photolithography,a vapor deposition, a droplet discharging method or the like. Althoughthe antenna 550 is formed using a single-layer conductive film in theembodiment mode, it may be formed by laminating plural conductive films.For example, a wiring formed by using Ni or the like is coated with Cuby electroless plating to form the antenna 550.

By using a printing method or a droplet discharging method, the antenna550 can be formed without using a mask for light-exposure. Differingfrom the photolithography in which loss of materials is caused byetching, the droplet discharging method and the printing method canutilize materials efficiently. In addition, the manufacturing cost of IDchips can be reduced since an expensive mask for light-exposure is notrequired.

When using the droplet discharging method or the various kinds ofprinting methods, for example, a conductive particle obtained by coatingCu with Ag can also be used. In the case where the antenna 550 is formedby a droplet discharging method, the surface of the bank 546 isdesirably exposed to a treatment for increasing the adhesion of theantenna 550.

In order to increase the adhesion, for example, the following methodscan be cited: a metal or a metal Compound that can improve the adhesionof a conductive film or an insulating film due to catalytic action isattached to the surface of the bank 546; an organic insulating film, ametal, and a metal compound each of which is well-adhered to aconductive film or an insulating film to be formed are attached to thesurface of the bank 546; and the surface of the bank 546 is subjected toplasma processing under atmospheric pressure or reduced pressure tochange the properties of the surface thereof. As the metal, which iswell-adhered to the conductive film or the insulating film, titanium,titanium oxide, 3d transition elements such as Sc, Ti, V, Cr, Mn, Fe,Co, Ni, Cu, Zn and the like can be cited. As the metal compound, oxide,nitride, oxynitride and the like of the above-mentioned metals can becited. As the above-described organic insulating film, polyimide,siloxane resin and the like are cited as examples.

When the metal or the metal compound to be attached to the bank 546 hasconductivity, the sheet resistance is controlled so as not to hinder thenormal operation of the antenna. Specifically, the average thickness ofthe metal or metal compound having conductivity may be controlled to be,for example, 1 to 10 nm. The metal or the metal compound may be partlyor entirely oxidized to be insulated. Alternatively, in a region otherthan a region in which the adhesion is intended to be improved, theattached metal or metal compound may be selectively removed by etching.The metal or the metal compound may be selectively attached to a certainregion by the droplet discharging method, the printing method, thesol-gel method, etc. rather than attaching it in advance onto the entiresurface of the substrate. It is not necessary for the metal or the metalcompound to have a completely continuous shape like a film on thesurface of the bank 546 and may be dispersed to some extent.

A protective film may be formed to cover the light-emitting element 549or the antenna 550 after forming the light-emitting element 549 and theantenna 550. A film that prevents a material such as water or oxygen,which are causes of deterioration of a light emitting element frompenetrating more than other insulating films is used for the protectivefilm. Typically, a DLC film, a carbon nitride film, a silicon nitridefilm formed by an RF sputtering or a CVD method, or the like ispreferably used. A film in which a carbon nitride film and a siliconnitride film are laminated, a film in which polystyrene is laminated, orthe like may be used for the protective film In addition, it is possibleto use a laminated layer of the film that prevents water or oxygen frompenetrating and a film that transmits more water or oxygen than theabove described film but is low in internal stress as the protectivefilm. A silicon nitride is employed in this embodiment mode. When asilicon nitride film is used as the protective film, a rare gas elementsuch as Ar may be contained in a reaction gas and may be mixed into theprotective film to form a fine protective film with a low depositiontemperature.

As shown in FIG. 9C, an adhesive agent 551 is applied over the bank 546to cover the light-emitting element 549 and the antenna 550, then thecover material 552 is attached thereto. The cover material 552 can beformed using the same material as the second substrate 545. Thethickness of the adhesive agent 551 may be e.g., 10 to 200 μm.

A material that can attach the cover material 552 and both of the bank546 and the antenna 550 to one another is used for the adhesive agent551. As the adhesive agent 551, for example, various types of curingadhesive agents including a reactive curing adhesive agent, a thermalcuring adhesive agent, a light curing adhesive agent such as anultraviolet curing adhesive agent, an anaerobic curing adhesive agentand the like can be used.

Through the above described steps, an ID chip is completed. By themanufacturing method, an extremely thin integrated circuit that is 0.3μm to 3 μm typically, 2 μm in total thickness can be formed between thesecond substrate 545 and the cover material 552. The thickness of theintegrated circuit includes various insulating films and interlayerinsulating films formed between the adhesive agent 544 and the adhesiveagent 551, in addition to the thickness of the semiconductor elementitself. The area of the integrated circuit included in an ID chip can be5 mm×5 mm (25 mm square) or less, preferably, about 0.3 mm×0.3 mm (0.09mm square) to 4 mm×4 mm (16 mm square).

The mechanical strength of an ID chip can be enhanced by locating theintegrated circuit in a position closer to the center between the secondsubstrate 545 and the cover material 552. Specifically, when thedistance between the second substrate 545 and the cover material 552 isd, it is preferable to control the thickness of the adhesive agents 544and 551 so that the distance x between the center 0 in the thicknessdirection of the integrated circuit and the second substrate 545 canfulfill formula 1 shown below.

$\begin{matrix}{{{\frac{1}{2}d} - {30\mspace{14mu} {µm}}} < x < {{\frac{1}{2}d} + {30\mspace{14mu} {µm}}}} & {{Formula}\mspace{14mu} 1}\end{matrix}$

More preferably, the thickness of the adhesive agents 544 and 551 arecontrolled to fulfill formula 2 as shown below.

$\begin{matrix}{{{\frac{1}{2}d} - {10\mspace{14mu} {µm}}} < x < {{\frac{1}{2}d} + {10\mspace{14mu} {µm}}}} & {{Formula}\mspace{14mu} 2}\end{matrix}$

As shown in FIG. 10, the thickness of the base film 502, the firstinterlayer insulating film 533, the second interlayer insulating film534 or the bank 546 may be adjusted so that the distance tuner, betweenthe island-like semiconductor film of the TFT and the base film of thelower part, and the distance t between the island-like semiconductorfilm and the bank 546, in the integrated circuit are equal or almostequal. By locating the island-like semiconductor film in the center ofthe integrated circuit, the stress applied on the semiconductor layercan be released and generation of cracks can be prevented.

In FIG. 9C, an example of employing the cover material 552 is shown, butthe present invention is not limited to this structure. For example, thestep shown in FIG. 9B may be the last step or a layer for protecting theantenna 550 and the light-emitting element 549 may be formed after thestep shown in FIG. 9B, thereby completing the integrated circuit.

The method for separating the integrated circuit from the substrate byproviding the separation layer between the first substrate 500 that ishigh heat resistant and the integrated circuit and removing theseparation layer by etching is shown in the embodiment mode, however,the method for manufacturing an ID chip according to the presentinvention is not limited thereto. For example, a metal oxide film may beprovided between the high heat resistant substrate and the integratedcircuit and the metal oxide film may be crystallized to be weakened sothat the integrated circuit is separated from the substrate.Alternatively, a separation layer made from an amorphous semiconductorfilm containing hydrogen may be provided between the high heat resistantsubstrate and the integrated circuit and the separation layer may beremoved by laser irradiation so that the integrated circuit may beseparated from the substrate. Alternatively, the high heat resistantsubstrate over which the integrated circuit is form may be mechanicallyeliminated or removed by etching using a solution or a gas so that theintegrated circuit may be separated from the substrate.

When organic resin is used as the adhesive agent 544 in contact with thebase film 502, to ensure the flexibility of the ID chip, it is possibleto prevent an alkaline metal such as Na or an alkaline earth metal fromspreading into the semiconductor film from the organic resin by using asilicon nitride film or a silicon nitride oxide film as the base film502.

When an ID chip is attached to an object having a curved surface, whichis created by a bus bar on a conical surface, a cylindrical surface orthe like, and the second substrate 545 of the ID chip is also curved, itis preferable that the direction of the bus bar is the same as amovement direction of carriers of the TFTs 529 to 532. According to thestructure, adverse affects due to bending of the second substrate 545 tothe characteristics of the TFTs 529 to 532 can be prevented. Thepercentage of area in the integrated circuit occupied by the island-likesemiconductor film is set 1 to 30%, thereby suppressing adverse affectsto the characteristics of the TFTs 529 to 532 even when the secondsubstrate 545 is bent.

This embodiment mode describes the example in which the antenna and theintegrated circuit are formed on the same substrate. However, thepresent invention is not limited to this structure. An antenna formed ona substrate may be attached to an integrated circuit fored on anothersubstrate to electrically connect with each other. In this embodimentmode, the example of forming both the antenna 550 and the light-emittingelement 549 over the bank 546 is shown. However, the present inventionis not limited to this structure and the antenna 550 and thelight-emitting element 549 may be formed over different layers.

In general, ID chips in many cases use radio waves with a frequency of13.56 MHz or 2.45 GHz. Therefore, it is extremely important forexpanding the versatility of ID chips that an ID chip is formed so thatradio waves of these frequencies can be detected.

The ID chip of this embodiment mode has the advantage that radio wavesare less shielded therein as compared with in an ID chip formed by usinga semiconductor substrate, and thus signal attenuation due to shieldedradio waves can be prevented. Therefore, since a semiconductor substrateis not needed, the cost of the ID chip can be drastically reduced. Forexample, the case of using a silicon substrate with a diameter of 12inches is compared with the case of using a glass substrate with a sizeof 730×920 mm² The silicon substrate has an area of about 73000 mm²whereas the glass substrate has an area of about 672000 mm², that is,the glass substrate is about 9.2 times larger than the siliconsubstrate. On the glass substrate with an area of about 672000 mm²,about 672000 ID chips each having an area of 1 mm square can be formedwhen margin for cutting the substrate is not taken into account, whichis about 9.2 times more than the ID chips formed on the siliconsubstrate. In the case of using the glass substrate with a size of730×920 mm², which requires fewer manufacturing steps, facilityinvestment cost for mass production of ID chips can be reduced byone-third of the case in which the silicon substrate with a diameter of12 inches is used. Further, according to the present invention, after anintegrated circuit is separated from a glass substrate, the glasssubstrate can be reused. Therefore, in the case of using the glasssubstrate, the cost can be significantly reduced when compared to thecase of using the silicon substrate, even when the cost of compensatingfor a broken glass substrate or cleaning a surface of the glasssubstrate is taken into account. Even if a glass substrate is not reusedand discarded, a glass substrate with a size of 730×920 mm² costs abouthalf as much as a silicon substrate with a diameter of 12 inches. As aresult, it is apparent that the cost of an ID chip can be reduceddrastically.

Thus, an ID chip using a glass substrate with a size of 730×920 mm²costs about only one-thirtieth as much as an ID chip using a siliconsubstrate with a diameter of 12 inches. Since the ID chip is expected tobe used as a disposable one, the ID chip of the present invention, whichcan cost much less, is quite effective for such an application.

In this embodiment mode, the example in which the integrated circuit isseparated and attached to a flexible substrate is shown. However, thepresent invention is not limited to this structure. For example, anintegrated circuit is not necessarily separated if a heat resistantsubstrate such as a glass substrate, which can resist a heat treatmentduring the manufacturing steps of the integrated circuit, is used.

In addition, the IC card of the present invention can be formed asreferred to in the above manufacturing method. Note that when the ICcard has a display device, the display device may be formed separatelyfrom the integrated circuit and attached to the second substrate or thedisplay device may be formed with the integrated circuit and attached tothe second substrate.

Embodiment 1

Embodiment 1 describes a structure of an ID chip in which an antenna andan integrated circuit, each formed over different substrates, areelectrically connected to each other, which is different from EmbodimentModes.

As shown in FIG. 11A, a bank 1200 having an opening portion is formedand parts of each wiring 1201 and 1202 are exposed in the openingportion in the ID chip of this embodiment.

An adhesive agent 1207 is formed over the bank 1200 to cover a terminal1203, and a cover material 1208 is attached to the bank 1200 by theadhesive agent 1207. Anisotropic conductive resin can be used for theadhesive agent 1207.

An antenna 1209 is formed in advance on the cover material 1208. Theantenna 1209 is formed on the side opposite to the bank 1200 of thecover material 1208. A portion of the antenna 1209 is exposed on theterminal 1203 side through a contact hole formed in the cover material1208. Note that the antenna 1209 may be formed on the bank 1200 side ofthe cover material 1208. The antenna 1209 and the terminal 1203 can beelectrically connected by using anisotropic conductive resin as theadhesive agent 1207.

The anisotropic conductive resin is a material in which a conductivematerial is dispersed in a resin. The following examples can be used asthe resin: a thermal curing resin such as an epoxy resin, a urethaneresin, and an acrylic resin; a thermoplastic resin such as apolyethylene resin and a polypropylene resin; a siloxane resin; and thelike. As the conductive material, for example, a plastic particle suchas polystyrene and epoxy that is plated by Ni, Au or the like; a metalparticle such as Ni, Au, Ag, solder; particulate or fibrous carbon,fibrous Ni plated by Au; and the like can be used. The size of theconductive material is desirably determined in accordance with thedistance between the antenna 1209 and the terminal 1203.

The antenna 1209 and the terminal 1203 may be pressure-bonded to eachother by applying ultrasonic waves to the anisotropic conductive resin,or pressure bonded to each other by curing the anisotropic conductiveresin using irradiation with ultraviolet light.

Although this embodiment shows the example of electrically connectingthe antenna 1209 and the terminal 1203 with the adhesive agent 1207 madefrom the anisotropic conductive resin, the present invention is notlimited to the structure. The antenna 1209 and the terminal 1203 may beelectrically connected by pressure bonding an anisotropic conductivefilm as the substitute for the adhesive agent 1207.

Although the embodiment shows the example in which the integratedcircuit is separated and then attached to the flexible substrate, thepresent invention is not limited to the structure. For example, whenusing a substrate that can withstand a heat treatment such as a glasssubstrate in the process of manufacturing the integrated circuit, theintegrated circuit is not necessarily separated. FIG. 11B is a crosssectional view showing one mode of the ID chip that is formed by using aglass substrate.

In the ID chip shown in FIG. 11B, a glass substrate is used as thesubstrate 1210. No adhesive agent is sandwiched between semiconductorelements 1211 to 1214 used for an integrated circuit and the substrate1210, and as the result thereof, the substrate 1210 and the base film1215 are formed to be in contact with each other. In the structure,there is no possibility that the alkali metal such as Na, alkali earthmetal, water and the like penetrate into a semiconductor film includedin the semiconductor elements 1211 to 1214.

Embodiment 2

Embodiment 2 describes an example of a photodiode used in an ID chip oran IC card of the present invention.

FIG. 12A shows a cross-section of an ID chip or an IC card of thisembodiment. In FIG. 12A, a photodiode 1500 is formed over the secondinterlayer insulating film 1501, and a TFT 1502 for controlling drive ofthe photodiode 1500 is covered by the first interlayer insulating film1503 and the second interlayer insulating film 1501. Although the TFT1502 is covered by two interlayer insulating films, that is, the firstinterlayer insulating film 1503 and the second interlayer insulatingfilm 1501, this embodiment is not limited to this structure. The TFT1502 may also be covered by a single layer of an interlayer insulatingfilm or three or more layers of interlayer insulating films.

The photodiode 1500 includes a cathode 1504 formed over the secondinterlayer insulating film 1501, a photoelectric conversion layer 1505formed over the cathode 1504 which conducts photoelectric conversion,and an anode 1506 formed over the photoelectric conversion layer 1505.Specifically, the cathode 1504 can be formed of an alkali metal such asLi or Cs; an alkali-earth metal such as Ca, Sr, or Mg; an alloyincluding these (such as Mg:Ag, Al:Li, or Mg:In); a chemical compound ofthese (such as CaF₂ or CaN); or a rare-earth metal such as Yb or Er, forexample. The photoelectric conversion layer 1505 can be formed by usinge.g., an amorphous silicon film containing hydrogen. In addition, theanode 1506 may be formed of a light-transmitting conductive oxidematerial such as the indium tin oxide (ITO), zinc oxide (ZnO), indiumzinc oxide (IZO), or gallium-doped zinc oxide (GZO). Moreover, the anodemay be formed of indium tin oxide including ITO and silicon oxide(ITSO), or indium oxide including silicon oxide in which zinc oxide(ZnO) is further mixed in the range of 2 to 20%.

Note that the cathode 1504, the photoelectric conversion layer 1505 andthe anode 1506 each may have a single layer structure or a laminatedstructure.

As shown in FIG. 12B, a shielding film 1513 for shielding light isprovided on the side opposite to the substrate 1510 with respect to thephotodiode 1511. Thus, the direction of light that enters the photodiode1511 can be limited. A metal film, a resin added with a pigment, or thelike that can shield light can be used for the shielding film 1513.

In FIG. 12B, light emitted from the light-emitting element 1512 isdirected toward the side opposite to the substrate and the shieldingfilm 1513 is formed so that light from the substrate 1510 side entersthe photodiode 1511 preferentially. However, the present embodiment isnot limited to this structure. The position for forming the shieldingfilm 1513 is not limited to the position shown in FIG. 12B. In addition,as for the direction of the light emitted from the light-emittingelement 1512, light may be emitted toward the substrate 1510 withoutbeing limited to the structure shown in FIG. 12B.

Note that the shielding film 1513 can be formed even if a photodiodehaving the structure shown in Embodiment Modes is used.

The photodiode used in an ID chip or an IC card of the present inventionis not limited to the structure of this embodiment.

This embodiment can be combined with Embodiment 1.

Embodiment 3

A structure of an ID chip or an IC card in the case of forming a wiringconnected to a TFT and an antenna together by patterning one conductivefilm will be explained with reference to FIG. 13A. FIG. 13A is a crosssectional view of the ID chip or the IC card according to thisembodiment.

In FIG. 13A, reference numeral 1401 denotes a TFT for controlling theoperation of a light-emitting element 1409. The TFT 1401 includes anisland-like semiconductor film 1402, a gate insulating film 1403 incontact with the island-like semiconductor film 1402 and a gateelectrode 1404 that overlaps the island-like semiconductor film 1402with the gate insulating film 1403 interposed therebetween. The TFT 1401is covered with a first interlayer insulating film 1405 and a secondinterlayer insulating film 1406. In this embodiment, the TFT 1401 iscovered with two interlayer insulating films, that is, the firstinterlayer insulating film 1405 and the second interlayer insulatingfilm 1406. However, this embodiment is not limited to this structure.The TFT 1401 may be covered with a single layer or three or more layersof interlayer insulating films.

A wiring 1407 formed on the second interlayer insulating film 1406 isconnected to the island-like semiconductor film 1402 through a contacthole formed in the first interlayer insulating film 1405 and the secondinterlayer insulating film 1406.

An antenna 1408 is formed over the second interlayer insulating film1406. A conductive film is formed over the second interlayer insulatingfilm 1406 and patterned to form the wiring 1407 and the antenna 1408. Byforming the antenna 1408 along with the wiring 1407, the number of stepsfor manufacturing the ID chip or IC card can be reduced.

Next, a structure of an ID chip or an IC card in the case of forming agate electrode of a TFT and an antenna by patterning one conductive filmwill be explained with reference to FIG. 13B. FIG. 13B is a crosssectional view of the ID chip or the IC card according to thisembodiment.

In FIG. 13B, reference numeral 1411 denotes a TFT for controlling theoperation of a light-emitting element 1419. The TFT 1411 includes anisland-like semiconductor film 1412, a gate insulating film 1413overlapping the island-like semiconductor film 1412, and a gateelectrode 1414 that overlaps the island-like semiconductor film 1412with the gate insulating film 1413 interposed therebetween. An antenna1418 is formed over the gate insulating film 1413. A conductive film isformed over the gate insulating film 1413 and patterned to form the gateelectrode 1414 and the antenna 1418. By forming the antenna 1418 alongwith the gate electrode 1414, the number of steps for manufacturing theID chip or IC card can be reduced.

In this embodiment mode, the example in which the integrated circuit isseparated and attached to a substrate that is prepared separately isshown. However, the present invention is not limited to this structure.For example, an integrated circuit is not necessarily separated if aheat resistant substrate that can resist a heat treatment in themanufacturing steps of the integrated circuit, such as a glasssubstrate, is used.

Embodiment 4

Embodiment 4 describes a cross-sectional structure of a pixel in thecase that a TFT controlling the operation of a light-emitting element isp-type with reference to FIGS. 14A to 14C. Note that, in FIGS. 14A to14C, one (a first electrode) of two electrodes included in thelight-emitting element, which is directly or electrically connected to aTFT, is an anode, and the other electrode (a second electrode) thereofis a cathode, but the first electrode may be a cathode and the secondelectrode may be an anode.

FIG. 14A shows a cross-sectional view of a pixel in the case that a TFT6001 is p-type, and light emitted from a light-emitting element 6003 isextracted from a first electrode 6004 side. In FIG. 14A, the firstelectrode 6004 of the light-emitting element 6003 is electricallyconnected to the TFT 6001 through a wiring 6009. However, the presentinvention is not limited to this structure. A part of the wiring 6009that is directly connected to the IP I 6001 may be used as the firstelectrode 6004.

The TFT 6001 is covered with a first interlayer insulating film 6007 anda second interlayer insulating film 6002. Although in FIG. 14A, the TFT6001 is covered by two interlayer insulating films, that is, the firstinterlayer insulating film 6007 and the second interlayer insulatingfilm 6002, the present invention is not limited to this structure. TheTFT 6001 may be covered with a single layer of interlayer insulatingfilm, or three or more layers of interlayer insulating films.

A bank 6008 having an opening portion is formed over the secondinterlayer insulating film 6002. A portion of the first electrode 6004is exposed in the opening portion of the bank 6008, and the firstelectrode 6004, an electroluminescent layer 6005 and a second electrode6006 are stacked sequentially.

In FIG. 14A, the first electrode 6004 is an anode, and the secondelectrode 6006 is a cathode. Materials suitable for each the anode andthe cathode can be referred to in Embodiment Modes. Note that the firstelectrode 6004 is formed by using a material or a thickness that cantransmit light. The second electrode 6006 is formed by using a materialor a thickness that can reflect or shield light.

The electroluminescent layer 6005 is formed to have a single or aplurality of layers. In the case of a structure of plural layers, thefollowing layers in terms of carrier transporting properties may beclassified as a hole injecting layer, a hole transporting layer, a lightemitting layer, an electron transporting layer, an electron injectinglayer and the like. The hole injecting layer, the hole transportinglayer, the light emitting layer, the electron transporting layer and theelectron injecting layer are stacked in this order on the firstelectrode 6004, when the electroluminescent layer 6005 has, in additionto the light emitting layer, any of the following: the hole injectinglayer, the hole transporting layer, the electron transporting layer andthe electron injecting layer. Note that the boundary of each layer isnot necessarily distinct and the boundary can not be distinguishedclearly in some cases since the materials fowling the respective layersare partially mixed into the adjacent layers. Each of the layers may beformed of an organic material or an inorganic material. As for theorganic material, any one of a high molecular weight material, a mediummolecular weight material and a low molecular weight material can beemployed. Note that the medium molecular weight material means a lowpolymer in which the number of repeated structural units (the degree ofpolymerization) is about 2 to 20. There is no clear distinction betweenthe hole injecting layer and the hole transporting layer, and both ofthem inevitably have a hole transporting property (hole mobility). Thehole injecting layer is in contact with the anode, and the layer incontact with the hole injecting layer is distinguished as the holetransporting layer for convenience. The same applies to the electrontransporting layer and the electron injecting layer. A layer in contactwith the cathode is called the electron injecting layer while a layer incontact with the electron injecting layer is called the electrontransporting layer. The light emitting layer may have the function ofthe electron transporting layer in some cases, and it is thereforecalled a light emitting electron transporting layer.

In the case of the pixel shown in FIG. 14A, light emitted from the lightemitting element 6003 can be extracted from the first electrode 6004side as shown by the outlined arrow.

FIG. 1413 illustrates a cross-sectional view of a pixel in the casewhere a TFT 6011 is p-type and light emitted from a light emittingelement 6013 is extracted from a second electrode 6016 side. In FIG.14B, a portion of a wiring that is directly connected to the TFT 6011 isused as a first electrode 6014. However, the present invention is notlimited to this structure. The first electrode 6014 of thelight-emitting element 6013 may be electrically connected to the TFT6011 through a wiring formed separately.

An electroluminescent layer 6015 and the second electrode 6016 arestacked sequentially over the first electrode 6014. In FIG. 14B, thefirst electrode 6014 is an anode and the second electrode 6016 is acathode. Materials suitable for each the anode and the cathode can bereferred to in Embodiment Modes. Note that the first electrode 6014 isformed by using a material or a thickness that can reflect or shieldlight. The second electrode 6016 is formed by using a material or athickness that can transmit light.

The electroluminescent layer 6015 can be formed in the same way as theelectroluminescent layer 6005 shown in FIG. 14A. In the case of thepixel shown in FIG. 14B, light emitted from the light emitting element6013 can be extracted from the second electrode 6016 side as shown bythe outlined arrow.

FIG. 14C illustrates a cross-sectional view of a pixel in the case wherea TFT 6021 is p-type, and light emitted from a light emitting element6023 is extracted from opposite sides of a first electrode 6024 and asecond electrode 6026. Although FIG. 14C illustrates the structure inwhich the first electrode 6024 of the light emitting element 6023 iselectrically connected to the TFT 6021 through a wiring 6029, thepresent invention is not limited to this structure. A part of the wiring6029 that is directly connected to the TFT 6021 may be used as the firstelectrode 6024.

An electroluminescent layer 6025 and the second electrode 6026 arestacked sequentially over the first electrode 6024. In FIG. 14C, thefirst electrode 6024 is an anode and the second electrode 6026 is acathode. Materials suitable for each the anode and the cathode can bereferred to in Embodiment Modes. Note that the first electrode 6024 andthe second electrode 6026 are each formed by using a material or athickness that can transmit light.

The electroluminescent layer 6025 can be formed in the same way as theelectroluminescent layer 6005 shown in FIG. . In the case of the pixelshown in

FIG. 14C, light emitted from the light emitting element 6023 can beextracted from opposite sides of the first electrode 6024 and the secondelectrode 6026 as shown by the outlined arrows.

In this embodiment, the TFTs 6001, 6011 and 6021 each have a structurehaving two gate electrodes (a double gate structure) in which two TFTsare connected serially. However, this embodiment is not limited to thisstructure. A single gate structure including one gate electrode or amulti-gate structure having three or more gate electrodes in which threeor more TFTs are connected serially may be employed.

Embodiment 5

Embodiment 5 describes a cross-sectional structure of a pixel when a TFTcontrolling the operation of a light-emitting element is n-type, withreference to FIGS. 15A to 15C. Note that regarding two electrodes of thelight-emitting element, the case where one electrode (a first electrode)directly or electrically connected to a TFT is a cathode and the otherelectrode (a second electrode) is an anode, is shown in FIGS. 15A to15C, but the first electrode may be an anode and the second electrodemay be a cathode.

FIG. 15A shows a cross-sectional view of a pixel when a TFT 6031 isn-type, and light emitted from a light-emitting element 6033 isextracted from a first electrode 6034 side. In FIG. 15A, the firstelectrode 6034 of the light-emitting element 6033 is electricallyconnected to the TFT 6031 through a wiring 6039. However, the presentinvention is not limited to this structure. A part of the wiring 6039that is directly connected to the TFT 6031 may be used as the firstelectrode 6034.

An electroluminescent layer 6035 and a second electrode 6036 are stackedsequentially over the first electrode 6034. In FIG. 15A, the firstelectrode 6034 is a cathode and the second electrode 6036 is an anode.Materials suitable for each the anode and the cathode can be referred toin Embodiment Modes. Note that the first electrode 6034 is formed byusing a material or a thickness that can transmit light. The secondelectrode 6036 is formed by using a material or a thickness that canshield or reflect light.

The electroluminescent layer 6035 can be formed in the same way as theelectroluminescent layer 6005 shown in FIG. 14A. Note that an electroninjecting layer, an electron transporting layer, a light-emitting layer,a hole transporting layer and a hole injecting layer are laminated inthis order over the first electrode 6034, if the electroluminescentlayer 6035 includes any of the following: a hole injecting layer, a holetransporting layer, an electron transporting layer and an electroninjecting layer in addition to a light-emitting element.

In the case of the pixel shown in FIG. 15A, light emitted from the lightemitting element 6033 can be extracted from the first electrode 6034side as shown by the outlined arrow.

FIG. 15B illustrates a cross-sectional view of a pixel in the case wherea TFT 6041 is n-type and light emitted from a light emitting element6043 is extracted from a second electrode 6046 side. In FIG. 15B, aportion of the wiring that is directly connected to the TFT 6041 is usedas a first electrode 6044. However, the present invention is not limitedto this structure. The first electrode 6044 of the light-emittingelement 6043 may be electrically connected to the TFT 6041 through awiring formed separately.

An electroluminescent layer 6045 and the second electrode 6046 arestacked sequentially over the first electrode 6044. In FIG. 15B, thefirst electrode 6044 is a cathode and the second electrode 6046 is ananode. Materials suitable for each the anode and the cathode can bereferred to in Embodiment Modes. Note that the first electrode 6044 isformed by using a material or a thickness that can shield or reflectlight. The second electrode 6046 is formed by using a material or athickness that can transmit light.

The electroluminescent layer 6045 can be formed in the same way as theelectroluminescent layer 6035 shown in FIG. 15A. In the case of thepixel shown in FIG. 15B, light emitted from the light emitting element6043 can be extracted from the second electrode 6046 side as shown bythe outlined arrow.

FIG. 15C illustrates a cross-sectional view of a pixel in the case wherea TFT 6051 is n-type and light emitted from a light emitting element6053 is extracted from opposite sides of a first electrode 6054 and asecond electrode 6056. Although FIG. 15C illustrates a structure inwhich the first electrode 6054 of the light emitting element 6053 iselectrically connected to the TFT 6051 through a wiring 6059, thepresent invention is not limited to this structure. A part of the wiring6059 that is directly connected to the TFT 6051 may be used as the firstelectrode 6054.

An electroluminescent layer 6055 and the second electrode 6056 arestacked sequentially over the first electrode 6054. In FIG. 15C, thefirst electrode 6054 is a cathode and the second electrode 6056 is ananode. Materials suitable for each the anode and the cathode can bereferred to in Embodiment Modes. Note that the first electrode 6054 andthe second electrode 6056 are each formed by using a material or athickness that can transmit light.

The electroluminescent layer 6055 can be formed in the same way as theelectroluminescent layer 6035 shown in FIG. 15A. In the case of thepixel shown in FIG. 15C, light emitted from the light emitting element6053 can be extracted from opposite sides of the first electrode 6054and the second electrode 6056 as shown by the outlined arrows.

In this embodiment, the TFTs 6031, 6041 and 6051 each have a structurehaving two gate electrodes (a double gate structure) in which two TFTsare connected serially. However, this embodiment is not limited to thisstructure. A single gate structure including one gate electrode or amulti-gate structure having three or more gate electrodes in which threeor more TFTs are connected serially may be employed.

Embodiment 6

Embodiment 6 describes a structure of a TFT used in an ID chip or an ICcard of the present invention.

FIG. 16A shows a cross sectional view of TFT according to theembodiment. Reference numeral 701 represents an n-channel TFT; and 702,a p-channel TFT. The configuration of the n-channel TFT 701 will beexplained in detail as an example.

The n-channel TF 701 includes an island-like semiconductor film 705 tobe used as an active layer. The island-like semiconductor film 705includes two impurity regions 703 to be used as a source region and adrain region, a channel formation region 704 sandwiched between the twoimpurity regions 703, and two LDD (lightly doped drain) regions 710sandwiched between the impurity regions 703 and the channel formationregion 704. The n-channel TF 701 further includes a gate insulating film706 covering the island-like semiconductor film 705, a gate electrode707, and two sidewalls 708 and 709 made from insulating films.

Although the gate electrode 707 includes two conductive films 707 a and707 b in this embodiment, the present invention is not limited to thisconfiguration. The gate electrode 707 may include a single-layerconductive film or two or more layer conductive films. The gateelectrode 707 overlaps the channel formation region 704 of theisland-like semiconductor film 705 with the gate insulating film 706therebetween. The sidewalls 708 and 709 overlap the two LDD regions 710of the island-like semiconductor film 705 with the gate insulating layer706 therebetween.

For example, the sidewalls 708 can be formed by etching a silicon oxidefilm with a thickness of 100 nm whereas the sidewalls 709 can be formedby etching an LTO film (a low temperature oxide film) with a thicknessof 200 nm. In this embodiment, the silicon oxide film used for thesidewalls 708 is formed by a plasma CVD method and the LTO film used forthe sidewalls 709 is formed by a low pressure CVD method. Note thatalthough the silicon oxide film may contain nitrogen, the number ofnitrogen atoms is to be set lower than that of oxygen atoms.

After doping an n-type impurity to the island-like semiconductor film705 using the gate electrode 707 as a mask, the sidewalls 708 and 709are formed, and an n-type impurity element is doped to the island-likesemiconductor film 705 utilizing the sidewalls 708 and 709 as masks, sothat the impurity regions 703 and the LDD regions 710 can be formedseparately.

The p-channel TFT 702 has almost the same configuration as the n-channelTFT 701; however, only a structure of an island-like semiconductor film711 of the p-channel TFT 702 is different. The island-like semiconductorfilm 711 does not have an LDD region, but includes two impurity regions712 and a channel formation region 713 sandwiched between the impurityregions. The impurity regions 712 are doped with a p-type impurity.Although FIG. 16A illustrates an example in which the p-channel TFT 702does not have an LDD region, the present invention is not limited tothis configuration. The p-channel TFT 702 may include an LDD region.

FIG. 16B shows a case where each TFT shown in FIG. 16A has sidewallswith single layer. An n-channel TFT 721 and a p-channel TFT 722 as shownin FIG. 16B each include the sidewalls with single layer 728 and 729,respectively. The sidewalls 728 and 729 can, for example, be made byetching a silicon oxide film with a thickness of 100 nm. In thisembodiment, the silicon oxide film used for the sidewall 728 and 729 areformed by a plasma CVD method. The silicon oxide film may containnitrogen; however, the number of nitrogen atoms is to be set lower thanthat of oxygen atoms.

FIG. 16C shows a structure of bottom-gate TFTs. Reference numeral 741denotes an n-channel TFT; and 742, a p-channel TFT. The n-channel TFT741 will be explained in detail as an example.

In FIG. 16C, the n-channel TFT 741 includes an island-like semiconductorfilm 745. The island-like semiconductor film 745 includes two impurityregions 743 used as a source region and a drain region, a channelformation region 744 sandwiched between the impurity regions 743, andtwo LDD (lightly doped drain) regions 750 sandwiched between the twoimpurity regions 743 and the channel formation region 744. The n-channelTFT 741 further includes a gate insulating film 746, a gate electrode747 and a protective film 748 which is made from an insulating film.

The gate electrode 747 overlaps the channel formation region 744 of theisland-like semiconductor film 745 with the gate insulating film 746therebetween. The gate insulating film 746 is formed after forming thegate electrode 747 and the island-like semiconductor film 745 is formedafter forming the gate insulating film 746.

The protective film 748 overlaps the gate insulating film 746 with thechannel formation region 744 therebetween.

The protective film 748, for example, can be formed by etching a siliconoxide film with a thickness of 100 nm. In this embodiment, the siliconoxide film is formed by a plasma CVD method as the protective film 748.Note that the silicon oxide film may contain nitrogen; however, thenumber of nitrogen atoms is to be set lower than that of oxygen atoms.

After doping an n-type impurity to the island-like semiconductor film745 utilizing a mask made from a resist, the protective film 748 isformed, and an n-type impurity is doped to the island-like semiconductorfilm 745 by utilizing the protective film 748 as a mask, so that theimpurity regions 743 and the LDD regions 750 can be formed separately.

Although the p-channel TFT 742 has almost the same structure as then-channel TFT 741, only the structure of the island-like semiconductorfilm 751 of the p-channel TFT 742 is different. The island-likesemiconductor film 751 does not include an LDD region, but includes twoimpurity regions 752 and a channel formation region 753 sandwichedbetween the two impurity regions 752. The impurity regions 752 are dopedwith a p-type impurity. Although FIG. 16C shows the example in which thep-channel TFT 742 does not have an I DD region, the present invention isnot limited to the structure. The p-channel TFT 742 may include an LDDregion.

This embodiment can be combined freely with Embodiments 1 to 5.

Embodiment 7

In this embodiment, a method for manufacturing plural ID chips or ICcards with the use of a large size substrate will be described.

An integrated circuit 401 and an antenna 402 are formed over a heatresistant substrate. Thereafter, the integrated circuit 401 and theantenna 402 are both separated from the heat resistant substrate andattached to a substrate 403, which has been separately prepared, with anadhesive agent 404 as shown in FIG. 17A. Although FIG. 17A shows a modein which a set of the integrated circuit 401 and the antenna 402 isattached to the substrate 403, the present invention is not limited tothis configuration. Alternatively, plural sets of the integrated circuit401 and the antenna 402, which are connected to each other, may beseparated from the heat resistant substrate and attached onto thesubstrate 403 at the same time.

As shown in FIG. 17B, a cover material 405 is attached to the substrate403 such that the integrated circuits 401 and the antennas 402 aresandwiched therebetween.

At this time, an adhesive agent 406 is applied over the substrate 403 soas to cover the integrated circuit 401 and the antenna 402. By attachingthe cover material 405 to the substrate 403, the state as shown in FIG.17C is obtained. Note that, in order to clearly show the positions ofthe integrated circuit 401 and the antenna 402, FIG. 17C illustrates theintegrated circuit 401 and the antenna 402 such that they are seenthrough the cover material 405.

As shown in FIG. 17D, the set of the integrated circuit 401 and theantenna 402 is separated from other sets of the integrated circuits 401and the antennas 402 by dicing or scribing, thereby completing an IDchip or an IC card 407.

This embodiment shows the example of separating the antennas 402 alongwith the integrated circuits 401, however, this embodiment is notlimited to this configuration. The antenna may be formed over thesubstrate 403 in advance and the integrated circuit 401 may be attachedto the substrate such that the integrated circuit 401 and the antenna402 are electrically connected to each other. Alternatively, afterattaching the integrated circuit 401 to the substrate 403, the antennamay be attached to the substrate such that the antenna is electricallyconnected to the integrated circuit 401. Alternatively, the antenna maybe formed over the cover material 405 in advance and the cover material405 may be attached onto the substrate 403 such that the integratedcircuit 401 can be electrically connected to the antenna.

When the substrate 403 and the cover material 405 are flexible, the IDchip or IC card 407 can be used while being stressed. In the presentinvention, the use of the stress relaxation film can allow pressureapplied to the ID chip or IC card 407 to be alleviated to some extent.In addition, by providing plural barrier films, stress to each barrierfilm can be suppressed, so that adverse effects to the characteristicsof the semiconductor element due to dispersion of the alkali metal, thealkali earth metal or water into the semiconductor element can beprevented.

Note that the ID chip using a glass substrate can be referred to as anIDG chip (identification glass chip) whereas the ID chip using aflexible substrate can be referred to as an IDF chip (identificationflexible ship).

This embodiment can be combined freely with Embodiments 1 to 6.

Embodiment 8

Embodiment 8 describes a shape of a groove to be formed when separatinga plurality of integrated circuits formed on one substrate. FIG. 18A isa top view of a substrate 603 over which a groove 601 is formed. FIG.1813 is a cross-sectional view of A-A′ from FIG. 18A.

An integrated circuit 602 is formed over a separation layer 604 which isformed on the substrate 603. The groove 601 is fowled between integratedcircuits 602 and formed deep enough to expose the separation layer 604.In this embodiment, the plurality of integrated circuits 602 are notcompletely but partially isolated by grooves 601.

Next, FIGS. 18C and 18D each show a mode where an etching gas is flowninto the groove 601 shown in FIGS. 18A and 18B to remove the separationlayer 604 by etching. FIG. 18C corresponds to a top view of thesubstrate 603 on which the groove 601 is formed. FIG. 18D corresponds toa cross-sectional view of A-A′ from FIG. 18C. It is assumed that theseparation layer 604 is etched from the groove 601 to a region denotedby a broken line 605. The plurality of integrated circuits 602 are notcompletely but partially isolated by grooves 601 and are partiallyconnected to each other as shown in FIGS. 18C and 18D. Therefore, it ispossible to prevent each integrated circuit 602 from moving as thesupport is lost after etching the separation layer 104.

After the mode shown in FIGS. 18C and 18D is formed, integrated circuits602 are separated from the substrate 603 by using a tape, a substrate orthe like attached with an adhesive agent, which is prepared separately.The plurality of integrated circuits 602 which have been separated fromthe substrate 603 are attached onto a support medium before or afterbeing sectioned from each other.

This embodiment describes an example of a manufacturing method of an IDchip or an IC card. A manufacturing method of an ID chip or an IC cardaccording to the present invention is not limited to the structuredescribed in this embodiment.

This embodiment can be freely combined with Embodiments 1 to 7.

Embodiment 9

When an ID chip of the present invention is fowled using a flexiblesubstrate, the ID chip is suitable for being attached to an objecthaving flexibility or a curved face.

When a memory such as a ROM that cannot be rewritten is fainted insideof an integrated circuit included in the ID chip of the presentinvention, forgery of the objects attached with the ID chip can beprevented. For example, the application of the ID chip of the presentinvention to foods in which their commodity values largely depend onproduction areas and producers is advantageous for inhibitingmislabeling of the production areas and producers at a low cost.

Specifically, the ID chip of the present invention can be used as the IDchip attached to tags having information about objects such as luggagetags, price tags and name tags. Also, the ID chip of the presentinvention itself may be utilized as such tags. For example, the ID chipmay be attached to certificates corresponding to documents that provefacts such as family registers, certificates of residence, passports,licenses, identification cards, member cards, surveyor certificates,credit cards, cash cards, prepaid cards, consultation cards and commuterpasses. In addition, for instance, the ID chip may be attached toportfolios corresponding to certificates that show property rights inprivate law such as bills, checks, carriage notes, cargo certificates,warehouse certificates, stock certificates, bond certificates, giftcertificates and deeds of mortgage.

FIG. 19A shows an example of a check 1301 attached with an ID chip 1302of the present invention. Although the ID chip 1302 is attached to theinside of the check 1301 in FIG. 19A, it may be provided to be exposedon the surface of the check.

FIG. 19B shows an example of a passport 1304 attached with an ID chip1303 of the present invention. Although the ID chip 1303 is attached tothe front page of the passport 1304 in FIG. 19B, it may be attached toanother page of the passport.

FIG. 19C shows an example of a gift certificate 1306 attached with an IDchip 1305 of the present invention. The ID chip 1305 may be attached toeither the inside of the gift certificate 1306 or on the surface thereofto be exposed.

The ID chip using an integrated circuit with TFTs is inexpensive andthin, and hence, the ID chip of the present invention is suitable for IDchips that are eventually discarded by consumers. In particular, whenthe ID chip is applied to products in which difference in price in unitsof several yen to several tens of yen significantly affects sales, apacking material having the inexpensive and thin ID chip of the presentinvention is very advantageous. The packing material is equivalent to asupport medium, such as a plastic wrap, a plastic bottle, a tray and acapsule, which can be shaped or has been shaped to wrap up an object.

A state of packing a boxed meal 1309 for sale by a packing material1308, which is attached with an ID chip 1307 of the present invention,is shown in FIG. 20A. By storing the price and the like of the productin an ID chip 1307, the cost for the boxed meal 1309 can be accountedfor by a register having functions of a reader/writer.

For example, the ID chips of the present invention may be attached to aproduct label so that the distribution process of the product ismanaged.

As shown in FIG. 20B, an ID chip 1311 of the present invention isattached to a support medium such as a product label 1310 with its rearface having viscosity. The label 1310 attached with the ID chip 1311 ispasted to a product 1312. Identification information about the product1312 can be read wirelessly from the ID chip 1311 attached to the label1310. Accordingly, management of distribution process of the productbecomes easier by the ID chip 1311.

In the case of using a nonvolatile memory, which can write informationtherein, as a memory of an integrated circuit included in the ID chip1311, information of the distribution process of the product 1312 can bestored. Stored information of the process in the production stage ofproducts can allow wholesalers, retailers and consumers to graspinformation about production areas, producers, dates of manufacture,processing methods and the like easily.

This embodiment can be freely combined with Embodiments 1 to 8.

1. (canceled)
 2. A semiconductor device comprising: a conductive layerconfigured to generate an alternating voltage based on a received radiowave; a light-receiving element configured to receive a first opticalsignal and generate a first electrical signal; an integrated circuitincluding: a rectification circuit configured to rectify the alternatingvoltage; and a power supply circuit configured to generate a powersupply voltage from rectified voltage and supply the power supplyvoltage to other circuits included in the integrated circuit, theintegrated circuit being configured to generate a second electricalsignal from the first electrical signal; and a light-emitting elementconfigured to receive the second electrical signal from the integratedcircuit and generate a second optical signal, wherein thelight-receiving element and the light-emitting element are not providedin the integrated circuit.
 3. The semiconductor device according toclaim 2, wherein the light-receiving element has a layer configured toconduct photoelectric conversion, and wherein the light-emitting elementhas an electroluminescent layer.
 4. The semiconductor device accordingto claim 2, wherein the integrated circuit, the light-emitting element,and the light-receiving element are formed on a substrate.
 5. Thesemiconductor device according to claim 4, wherein the substrate is aplastic substrate.
 6. The semiconductor device according to claim 2,wherein the conductive layer, the integrated circuit, the light-emittingelement, and the light-receiving element are formed on a substrate. 7.The semiconductor device according to claim 6, wherein the substrate isa plastic substrate.
 8. The semiconductor device according to claim 2,wherein the other circuits included in the integrated circuit comprise:a demodulation circuit configured to demodulate the first electricalsignal from the light-receiving element; and a logic circuit configuredto generate the second electrical signal.
 9. The semiconductor deviceaccording to claim 2, wherein the first optical signal is sent from areader/writer, and wherein the second optical signal is sent to thereader/writer.
 10. The semiconductor device according to claim 2,further comprising a display portion electrically connected to theintegrated circuit.
 11. A semiconductor device comprising: a conductivelayer configured to generate an alternating voltage based on a receivedradio wave; a light-receiving element configured to receive a firstoptical signal from a reader/writer and generate a first electricalsignal; an integrated circuit including: a rectification circuitconfigured to rectify the alternating voltage; and a power supplycircuit configured to generate a power supply voltage from rectifiedvoltage and supply the power supply voltage to other circuits includedin the integrated circuit, the integrated circuit being configured togenerate a second electrical signal from the first electrical signal;and a light-emitting element configured to receive the second electricalsignal transmitted from the integrated circuit, generate a secondoptical signal, and send the second optical signal to the reader/writer,wherein the conductive layer, the light-emitting element, and thelight-receiving element are not included in the integrated circuit, andwherein the integrated circuit, the light-emitting element, and thelight-receiving element are attached to a substrate with an adhesiveagent.
 12. The semiconductor device according to claim 11, wherein thesubstrate is a plastic substrate.
 13. The semiconductor device accordingto claim 11, wherein the conductive layer is attached to the substratewith the adhesive agent.
 14. The semiconductor device according to claim11, wherein the other circuits included in the integrated circuitcomprise: a demodulation circuit configured to demodulate the firstelectrical signal from the light-receiving element; and a logic circuitconfigured to generate the second electrical signal.
 15. Thesemiconductor device according to claim 11, further comprising a displayportion electrically connected to the integrated circuit.
 16. An IC cardcomprising: a conductive layer configured to generate an alternatingvoltage based on a received radio wave; a light-receiving elementconfigured to receive a first optical signal sent from a reader/writerand generate a first electrical signal; an integrated circuit including:a rectification circuit configured to rectify the alternating voltage;and a power supply circuit configured to generate a power supply voltagefrom rectified voltage and supply the power supply voltage to othercircuits included in the integrated circuit, the integrated circuitbeing configured to generate a second electrical signal from the firstelectrical signal; and a light-emitting element configured to receivethe second electrical signal and send a second optical signal to thereader/writer, wherein the conductive layer, the light-emitting element,and the light-receiving element are not provided in the integratedcircuit.
 17. The IC card according to claim 16, wherein the conductivelayer, the integrated circuit, the light-emitting element and thelight-receiving element are formed on a substrate.
 18. The IC cardaccording to claim 17, wherein the substrate is a plastic substrate. 19.The IC card according to claim 16, wherein the other circuits includedin the integrated circuit comprise: a demodulation circuit configured todemodulate the first electrical signal from the light-receiving element;and a logic circuit configured to generate the second electrical signal.20. The IC card according to claim 16, further comprising a displayportion electrically connected to the integrated circuit.